A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i.e., the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.

A central processing system which includes a plurality of units coupled over a common electrical bus for the transfer of information between any two units, includes one unit in which there is a shareable resource such as a memory for example. Apparatus is provided for any units to share such resource. Further apparatus is provided for enabling any of such units so sharing the resource to lock out any other unit which presents a specified control signal to the unit incorporating the resource.

A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i.e., the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.

A plurality of devices such as a disc storage device or printer for example are coupled over a common bus in a priority arrangement for providing interrupt servicing with a data processor. Each device may be in a state in which it either has (1) no present need for interrupt servicing, called the inactive state, or (2) a present need for interrupt servicing which need has not been acknowledged by the processor, called the wait state, or which need has been acknowledged by the processor, called the request state, or (3) it is presently enabled interrupt servicing with the processor, called the active state. Control means are shown which in combination with signals from the processor enable one or more of the devices to be in either state. The control means is coupled to respond in an improved manner to the state required and for example allows an active device to remain suspended in the active state while a device which has just gone to the active state is serviced, after which the suspended active state device is again serviced. The control means further includes means for changing the highest priority active device to its inactive state upon completion of its interrupt servicing without changing the state of any other devices.