An electrically and optically settable flip-flop is disclosed which includes, in integrated circuit form, an MOS flip-flop memory cell including first and second cross-coupled transistors coupled through respective third and fourth load transistors to a source of potential. A photodiode is connected from the cross connection between the output of said first transistor and the input of said second transistor to the substrate, whereby the photodiode is charged substantially to the source potential when the flip-flop is in its reset state with the first transistor cut off and the second transistor conductive. Interruption of the coupling of potential to the first transistor isolates the photodiode. Light energy directed to the photodiode renders it conductive to reduce the voltage at the input of the second transistor until its output turns on the first transistor, whereby the flip-flop is set. Restoring the coupling of bias potential to the first transistor causes the existing electrical state of the flip-flop to be maintained.
The present invention relates to an integrated single-channel MIS binary flip-flop circuit requiring only a single clock signal source. The clock signal varies between voltage levels adapted to enable transistors in the circuit and reference ground potential. By swinging the clock signal to reference ground potential, the requirement for either complementary MIS transistors or a combination of a clock signal supply and an inverted signal supply thereof is avoided.
A circuit is provided for resetting a digital logic circuit, such as a digital counter. A switch 16 provides a first signal when a predetermined condition has occcurred. A flip-flop 24 provides an output reset signal when the flip-flop is in a first state, in response to the first signal. The digital logic circuit to be reset 32 is coupled to the output of the flip-flop 24 for receiving its output reset signal. Feedback means 34, 36, 38 are coupled from the digital logic circuit 32 back to the flip-flop 24 for providing a signal to put the flip-flop into its other state whereby its output reset signal is terminated.
An electric power source for delivering a controllable voltage to a load. It has low power loss and is capable of acting as a programmable source of electric energy, one which can be used, for example, to furnish a very high-voltage output from a light-weight system. The power source is a modular type structure in which the apparatus is made up of a number of identical stages or modules connected in cascade. Each stage includes a voltage supply and floating reference voltage means connected to the supply. The voltage supply is connected to the output of the source through bilateral, solid-state switches along alternate electrically conductive paths which connect either one side or the other of the voltage supply to the output. A bistable circuit serves to control the bilateral switches, triggering of the bistable circuit being effected by radiation impinged upon light sensitive devices, the devices being connected to perform a set-reset type function of the circuit. The floating reference voltage provides a constant electric potential for switching purposes. The system can be used to step up a voltage, and a form thereof can be used to step a voltage down.
A digital photodetector circuit having a photosensing stage connected to a depletion mode field effect transistor forming an inverter stage, increased sensitivity is achieved by then coupling the output of the photo inverter to a second photo inverter whose photosensitive element serves as the active load of an enhancement mode field effect transistor in the inverter stage. The circuit is readily fabricated in integrated structures. The circuit performance may be adjusted for responsiveness to light sensitivity and to provide selectable electrical output signal level and impedance matching including bistable performance.
An improved means and method for forming an optical sensor within an integrated circuit structure is described. An epi-coated semiconductor wafer is masked and a cavity etched through the epi-layer to the underlying substrate. A dielectric sidewall is formed on the cavity sidewall and a substantially intrinsic semiconductor region, preferably grown by selective epitaxy, to refill the cavity. The upper surface of the intrinsic region is then heavily doped and contacted by a low resistance polysilicon layer which is substantially transparent to incoming light. The method forms a high sensitivity PIN photo-sensor having a thick space-charge region for efficient capture of the hole-electron pairs produced by the incoming light. The fabrication techniques are compatible with the processing requirements for other integrated circuit devices formed on the same chip and to which the PIN device is coupled without wire bonds, tabs, bumps or the like.
