A channel combining circuit for homodyne receivers or other systems emplog synchronous detection, which selects the output of either an in-phase detector or a quadrature phase detector. Each of two channels has an inverter circuit and two diodes making available at a common output terminal the most positive signal derived from either a positive or negative input signal from the detectors.

The invention relates to a clock recovery for a digital data signal. A phase detector receives the data signal and transmits it after clock recovery. A phase correcting device creates and transmits, by means of a number of auxiliary clock signals phase shifted with respect to each other and originating from an incoming clock signal (CK.sub.in), a recovered clock signal (CK.sub.out) for the data signal. The recovered clock signal is fed to the phase detector, which detects a phase position error, if any, between the data signal and its recovered clock signal and emits information regarding this to the phase correcting device. The phase correcting device includes a phase variation circuit arranged, if the phase position error deviates from zero and the phase position of the recovered clock signal is located between the phase positions of two of the auxiliary clock signals, to mix these two auxiliary clock signals with each other for forming an adjusted recovered clock signal with the same phase position as the data signal. The invention allows shifting of the phase of a clock signal continuously an arbitrary number of turns forwards or backwards without interruptions or discontinuities in the recovered clock signal. This implies that the invention can also be applied in the case of a difference occurring between the bit frequency of incoming data and the clock reference frequency.

An amplitude/phase discriminator network the entirety of which is integrated on the same (GaAs) semiconductor chip, obtains a quadrature phase split through the use of a pair of orthogonal phase generators each of which comprises an all-pass network coupled with a pair of differential amplifiers. An unknown signal of interest, the phase and amplitude of which are to be derived, is applied to one pair of all-pass networks, while a reference signal, the amplitude and phase of which are known, is applied to the other pair of all-pass networks. Four quadrature outputs produced by the differential amplifiers contained within the pair of orthogonal phase generators are selectively coupled to a signal combining stage comprised of a diode detector-low pass filter network. At the output of this network there are produced a set of output signals each of which has a magnitude component representative of the magnitudes of the unknown and reference signals and a phase component representative of the difference between the phases of the reference and unknown signals. Since the amplitude and phase of the reference signal are known, the amplitude and phase of the unknown signal can be readily determined.

An improved device for accurately phase or frequency shifting an input signal is disclosed incorporating a variable resistor extending between at least two known phase shifted values of said input signal.

A phase shifting network with multiple outputs between which a constant phase difference is maintained over a large frequency range. The configuration consists of a four branch all pass network which in turn consists of four similar all pass networks one in each branch. An in phase and an out of phase input signal are applied to this network and four signals in phase quadrature, 0.degree., 90.degree., 180.degree., and 270.degree. may be obtained from the network. The network is designed for operation at frequencies of micro and millimeter wavelengths and may be realized from resistive and capacitive elements fabricated upon a common monolithic substrate. A suitable substrate is gallium arsenide, permitting both passive and active elements to be formed and interconnected by lithographic techniques.