A current-switching-type flip-flop circuit device including first and second sections each comprising a first current-switching-type logic circuit comprising a first transistor forming an AND input gate and a second transistor carrying out a current switching operation jointly therewith, a second current-switching-type logic circuit provided with a third transistor forming an OR input gate to perform a flip-flop action, and a means for jointly connecting the collectors of the aforementioned second and third transistors.
A "D" flip-flop circuit is disclosed which includes a master latch having data input transistors coupled to the input terminals thereof and data transfer transistors connected to the output thereof. A slave latch is connected to the output terminals of the data transfer transistors. The flip-flop circuit utilizes a resistive feedback network coupled between the emitter terminals of the transistors of the master latch to facilitate increased output voltages and stable predictable operating conditions. The data input transistors are connected as emitter follower circuits for driving the master latch transistors in a common base configuration for maximizing the speed-power product of the circuit.
A transistorized master slave flip-flop having a threshold offset generated through circuit size variations. The area of the emitter regions of selected bipolar transistors in the master and slave flip-flops are varied to provide preferred sequencing and thereby avoid untimely changes in state. Adjusting the area of the emitter regions provides the necessary offset without increasing the number of components or circuit crossovers.
A d.c. triggered master-slave flip-flop circuit including a master flip-flop with a capacitive delay means at its input, and a slave flip-flop having its input connected to the output of the master flip-flop. A capacitive delay means is connected at the input of the slave flip-flop. The slave flip-flop controls the connections at the input of the master flip-flop in known manner. The two capacitive delay means, serve to make each flip-flop circuit immune to noise pulses and also eliminate multiple triggering caused by contact bounce when the circuit is controlled by mechanical contacts.
A binary divider circuit of the master-slave type. The master bistable flip-flop and the slave bistable flip-flop are arranged in series between the voltage supply lines so that current flows from one of the supply lines through one of the bistable circuits and then through the other of the bistable circuits into the other supply line. The series arrangement of the bistable circuits provides reduced power dissipation and increased switching speed. The disclosed embodiment further comprises diodes extending from one voltage supply line to the master bistable circuit for bypassing current around the slave bistable circuit and to the master bistable circuit so as to provide higher output power and/or faster switching speed for the master bistable circuit. The diodes further function as a voltage regulator for maintaining the voltage across each bistable circuit approximately constant to prevent the bistable circuits from interacting with each other as their respective impedances vary during switching operations.
Diode load emitter coupled logic circuits is described that utilizes forward biased diodes in the load circuits. The load circuits may be comprised of a single diode or two or more diodes connected in series. If a single diode is used in the load circuits, the slope factor of the diode must be greater than or equal to the slope factor of switching transistors in the logic circuit. External bias circuitry provides a bias current which can be varied for varying the frequency of operation of the logic circuit. High speeds at low power dissipations can be obtained since the switching transistors in the logic circuits do not switch completely on and off.
