A multiple instruction set processor and method dynamically activates one of a plurality of branch prediction processes depending upon which one of a multiple instruction set is operational. Shared branch history table structures are used and are indexed differently depending upon which instruction set is operational. The apparatus and method also allows switching between instruction set index generators for each of the plurality of instruction sets. Accordingly, different indexes to branch prediction data are used depending upon which of the plurality of instruction sets is operational. Shared memory may be used to contain branch prediction table data for instructions from each of the plurality of instruction sets in response to selection of an instruction set. Shared memory is also used to contain branch target buffer data for instructions from each of the plurality of instruction sets in response to selection of one of the instruction sets.

A multiprocessor system including firmware, which system is comprised of at least a plurality of central processing units and a main memory to be commonly occupied by all the central processing units. The main memory is composed of an operating system area and a firmware area. The firmware area is divided into a common firmware area utilized by all the central processing units and a plurality of independent prefix areas allotted to the central processing units. Each prefix area is operative as an interface port, for a respective central processing unit, between the operating system area and the common firmware area.

In a stored program type control system comprising a main memory device for storing data and an instruction word, an input/output device, and a central processing unit including a group of general registers and a program status word store, there are provided an instruction word system including a universal instruction word system, and a sequence instruction system containing a portion of the universal word system which control the content of a program status word, and selecting means responsive to an instruction word or an internal processing sequence at the time of interruption for selecting one or the other of the instruction word systems in accordance with data contained at a portion of the bits of the program status words indicates selection of either the universal status word system or the sequence instruction word system.

A numerical control system for machining centers, having a RAM and two groups of peripheral units, comprises two proessors interconnected by means of a common signal bus and adapted to operate simultaneously sharing access automatically to the RAM and to the peripheral units. One of the two processors is specialized for executing the computations relating to the interpolation of the path of the center of the tool with respect to the workpiece to be machined, while the second processor is specialized in control of the said peripherals. One group of peripherals comprises input and output means for data and programs and another group comprises a series of units for measuring and controlling the movement of the said tool and the said workpiece. The said processors are connected to the said memory and to the said input and output means by means of one signal bus, the measuring and control units are interconnected by means of a second signal bus connected to the first bus through a bidirectional interface.

A network of two or more microprogrammed digital processors is provided which permits operation of the individual processors independently or as linked processors for transferring real time control information at the micro level to establish microprogram control which is supplied from the processor that is processing the data determining the control sequence, resulting in dynamic master/slave relationships, with high performance, by eliminating the need to transfer data used to influence microprogramming sequencing. Next control memory address source designators within each processor, selectively enable microprogram control memory data sources of either processor when the control memory address busses of each processor are linked together. Upon unlinking of the address busses, each next control memory address source designator selectively enables a source only within its own processor, such as a branch address latch source, operation code mapping memory source, and a microsequencer source. Permanently linked processors provide a single processor network for achieving increased performance for multiple precision computations.