Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.

A logic comparator circuit and system for testing the operation of an operating logic circuit installed a powered system against the operation of a known good, or reference, logic circuit of the same type or style. This is accomplished by applying the power, return and input signals of the operating logic circuit to the reference logic circuit and then comparing the corresponding output signals of each to detect improper operation. The present invention makes the interconnection of the two logic circuits to the logic comparator simple by only requiring that the user designate which terminals of the logic circuits are for power and return. The present logic circuit is provided with means for automatically discriminating between input and output terminals of the two logic circuits, and for clamping a free floating terminal of the operating logic circuit so that it may be detected repeatably.

Level sensitive testing is performed on a generalized and modular logic system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using this scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.

An arrangement for checking contact betweena transmitter circuit situated upstream and a receiver circuit situated downstream, the contact being made to enable electrical signals corresponding to 1 and 0 logic states produced by the transmitter circuit to be transmitted in series to an input of the receiver circuit, is characterized in that it is formed by a first circuit situated upstream of the contact at the output of the transmitter circuit and a second circuit which is situated downstream of the contact at the input to the receiver circuit, the first circuit being designed to produce, at a first output connected to the second circuit, and if the contact is satisfactory, a current in a predetermined direction or the opposite direction in the presence of a signal representing a 1 or 0 logic state emitted by the transmitter circuit, the second circuit being designed to generate, at an output connected to the input of the receiver circuit, a signal corresponding to the logic state generated by the transmitter circuit when a current in the corresponding direction is emitted by the first circuit, the first circuit emitting a signal at a second output when the said current is present, this signal thus indicating that the contact is satisfactory.

An analogue circuit or unit under test is tested utilizing automatic test equipment and an interface unit to apply stimuli to the circuit the stimuli including supply potentials. A computer analyses the circuit as a network of nodes and modules to deduce a set of ranges of values at selected nodes, the ranges being determined from the set of the stimuli and a resultant set of test measurements, taken from nodes of the circuit by the interface and automatic test equipment, taking into account tolerances in the stimuli, the measurements and the nominal parameters of components of the circuit. If there is inconsistency among the derived ranges the computer treats as potentially faulty any module which could remove the inconsistency if the constraints imposed by that module were suspended. The computer controls an iterative, hierarchical process involving repetition of the sequence of steps using different sets of stimuli and/or measurements and/or different analyses of the circuit into nodes and modules, in particular with analysis in terms of successively smaller modules. In this way, the location of faults can be progressively narrowed down and corresponding output information can be given in a device such as a VDU or printer.