A ceramic package bearing an electrically conducting pattern and adapted to receive diminutive electronic components such as semiconductor elements includes metallic plugs in the conducting pattern to serve as islands to which internal lead connections to the semiconductor element are made. The plugs permit a high degree of flexibility in material selection for contact areas providing different metals without costly selective plating techniques. The resulting structure can be fabricated without any gold plating steps. Similar plugs may be used as islands to which external leads are connected.
An electronic circuit package in which a resistor network is readily installed and remains accessible for laser trimming after final assembly of the package. A substrate is provided having a circuit pattern on a surface thereof and terminating in electrical terminals for connection to external circuitry. The substrate includes an aperture about the periphery of which a plurality of contact pads are arranged and in connection with intended paths of the circuit pattern. A resistor network is formed on a surface of a smaller substrate, the resistors being connected to contact pads disposed about the periphery of the smaller substrate and configured to be in alignment with respective pads at the aperture of the larger substrate. The smaller substrate is placed on the larger substrate with the respective contact pads in alignment, and the engaged contact areas are bonded to mechanically retain the smaller substrate and to electrically interconnect the resistor network with the associated circuit pattern. The network remains accessible by way of the aperture in the larger substrate such that resistors can be laser trimmed after final assembly of the circuit package to achieve an intended and precise specification. After trimming, the network can be protected by an appropriate encapsulating layer.
A low cost package uses non-ceramic materials to environmentally seal an air chamber for an electronic component. The package includes a base formed by a plurality of essentially flat terminals molded in a polyphenylene sulfide resin so as to provide a planar surface for surface mounting to a circuit board. A component placement area on the base receives a cap which covers and seals the area from contaminants.
A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is electrically connected to the pattern and then the die and the inner bonds are hermetically sealed inside a cap that is smaller than the substrate so that the ends of the metallization pattern are exposed. The leads are then electrically connected, such as by solder or other technique to the exposed ends of the pattern.
A method for making multi-layer ceramic packages. The method provides for attaching contact pins to a ceramic substrate after the application of an intermediate metal layer and an outer metal layer. This eliminates plating the contact pins with an intermediate metal layer and an outer metal layer, thereby saving material and process time.
Package for an LSI chip having a plurality of contact pads comprising a carrier and a cover. The carrier is formed of a base of an insulating material and has a generally planar area for receiving the chip. A cooling stud is mounted on the base and can be provided with one or more removable cooling fins. The stud is mounted on the base opposite the area for receiving the chip. Spaced leads are carried by the base and have outer extremities which extend beyond the base in a direction away from the chip and are free of the carrier and have inner extremities which are in close proximity to the area for receiving the chip. A grounding bus is carried by the carrier to facilitate electrical checking of the package.
