A protection circuit is disclosed for protecting a P-channel enhancement-type metal oxide semiconductor transistor from rupturing due to static voltage building up between its gate and source electrodes. The protection circuit includes at least one N-channel depletion-type transistor having its drain and source electrodes connected between the gate and source electrodes of the enhancement-type transistor and its gate electrode coupled to a negative power supply terminal. A resistor is also included between the gate of the enhancement-type transistor and the terminal to which an input signal is applied. There is also included a diode, in shunt with the resistor and the depletion-type transistor, which is poled to be reverse biased by the input signal.
An input protection circuit which protects the gate of a MIS transistor from breakdown due to an excessively high voltage being applied thereto. The input protection circuit includes a first resistor and a second resistor connected in series between a input terminal and a gate of the MIS transistor, a first protection transistor provided between a first connecting point between the first and second resistors and one side of the power supply, and a second protection transistor provided between a second connecting point between the second resistor and the gate of the MIS transistor the other side of the power supply. The first protection transistor has a large mutual conductance gm, while the second protection transistor has a low breakdown voltage. With this input protection circuit, even when the gate breakdown voltage of the transistor to be protected is lower than the breakdown voltage of the first protection transistor, the gate electrode is kept at a voltage lower than the gate breakdown voltage by means of the second protection transistor having a lower breakdown voltage.
In a semiconductor device, in order to protect an interior of the device, protective circuits are provided. The protective circuits include a first circuit connected between the first terminal and a negative potential line, a second circuit connected between the first terminal and a ground potential line, and a third circuit connected between the ground potential line and a second terminal. The first circuit consists of a MOS transistor having a drain connected with the first terminal, a source connected with the negative potential line, and a gate connected with the first terminal or the negative potential line. The second circuit consists of a MOS transistor having a drain connected with the first terminal, a source connected with the ground potential line, and a gate connected with the first terminal or the ground potential line. The third circuit consists of a MOS transistor having a drain connected with the second terminal, a source connected with the ground potential line, and a gate connected with the second terminal or the ground potential line.
A first protecting insulated gate field effect (IGFE) transistor has a drain and a source connected respectively to a gate and a source of an IGFE transistor to be protected against overvoltages with the gate connected to an input through a resistor. A second protecting IGFE transistor higher in threshold voltage than the first protecting transistor has a source connected to the gate of the first protecting transistor and through another resistor to the source of the same transistor with its gate and drain operatively coupled to the input. The second protecting transistor first conducts in response to an overvoltage, applied to the input to decrease a voltage applied to the protected transistor and to conduct the first transistor. The conduction of the first transistor causes a voltage much decreased from the overvoltage to be applied to the protected transistor.
A muting circuit having a first resistor (R10) one end (a) of which is supplied with an input signal, a second resistor (R12) serially connected to the first resistor, a first transistor (14) whose collector is connected to the junction point (b) of the first and second resistors, and a second transistor (16) whose collector is connected to the other end (c) of the second resistor. The emitters of the first and second transistors are grounded, and the bases thereof are supplied with a DC muting signal. An output signal derived from the other end of the second resistor is attenuated when the muting signal is supplied to the first and second transistors.
A protected MOS transistor circuit includes an input MOS transistor and a depletion mode MOS transistor having a drain-source current path connected between ground and the gate of the input MOS transistor of obviating rupture of the gate oxide of the input MOS transistor when power is off. The depletion mode MOS transistor's gate receives a control signal only when power is on which renders the depletion mode MOS transistor nonconductive when power is on. The depletion mode MOS transistor is conductive when power is off.
