A method of coding in a plurality of unit coding circuit stages connected in cascade and of the same number as the coded bits comprises the steps of applying input signals to a first unit coding circuit stage, rectifying the input signals in the first stage, discriminating the polarity of the input signals in the first stage, successively applying the absolute value output signals of the first stage to the following stages for coding the absolute value signals, and converting the coded pulses of the following stages into series-coded pulses by discriminating the polarity of the input signals in the first stage in the coding period for the absolute value signals in the following stages.
The converter input i is connected through a comparator to the polarity bit output as well as to the input of a full-wave precision rectifier in the first quantization stage, which like further stages comprises an operational amplifier, a comparator and an exclusive OR gate, the output of which is connected to the output for the first bit. To the inverting input of the amplifier with the gain equal to 2 through the potentiometer a voltage -U.sub.o /2 is fed, (-U.sub.o, +U.sub.o) being the interval of the input voltage. The input of the rectifier is connector to the input i and the input of the rectifier in further stages is connected to the output of the operational amplifier in the previous stage. The second input of the exclusive OR gate is connected to the bit output of the previous stage.
An analog-to-digital converter comprises a series connected chain of encoder bits adapted to provide a digital output signal indicative of the amplitude of an applied sampled analog signal. A plurality of storage elements are connected respectively to the outputs of said encoder bits to receive the signals therefrom in response to a triggering signal from a triggering source. Delay elements are provided to delay progressively the storage of the output signal from respective ones of said encoder bits to compensate for propagation delay in the chain to effect storage of a digital signal indicative of an instantaneous level of the analog signal.
A coder for converting an input analog signal into a digital output signal containing first, second and other bit signals, includes a first coding circuit activated by the input analog signal to generate the output of the first coding circuit, a second coding circuit activated by the first bit signal to generate the second bit signal judged at a first time point, a feedback coding circuit energized by the output of the second coding circuit to generate the other bit signals; the first, second and other bit signal constituting the digital signal at an output terminal; the second and other bit signals subject to error due to the level of the output of the second coding circuit at the first time point; and a bit level comparison circuit comparing the second bit signal judged at the first time point and at a second time point succeeding the first time point for producing a comparison signal to correct the second and other bit signals, whereby the first bit signal and the corrected second and other bit signals after the second time point are included in the digital signal at the output terminal.
