An improved clock retiming system for pulse coded data is provided in which the clock signals are extracted from the encoded data and first and second signals of the same amplitude and frequency but of different phase are generated from the clock signals. First and second amplifiers having variable gains provide amplification for the first and second signals, respectively. The first and second amplified signals are summed to produce a third signal having a phase which is a function of the relative amplitudes of the first and second amplified signals. The original pulse encoded data is sampled with the third signal to produce the retimed data output. The original pulse encoded data is also utilized to sample the third signal. The resulting signal is filtered to provide a DC voltage feedback error signal indicative of the phase difference between the third signal and the original pulse encoded data. This feedback signal is translated into a pair of complementary signals forming inputs to the first and second amplifiers, respectively, to vary the variable gains thereof, oppositely thereby adjusting the phase of the third signal to correspond to the phase of the original pulse encoded data.

The phase of timing signals is compared with the phase of incoming digital signals to produce phase error signals and repeated phase corrections of the timing signals are made in accordance with the phase error signals. The phase corrections are initially delayed until phase error signals exceeding a predetermined magnitude persist for a predetermined interval of time. The corrections are removed without delay when the phase error signals are discontinued.

A device for removing extraneous signal components from signals containing a series of pulse components appearing on a signal transmission line at regular intervals and having a predetermined repetition frequency, wherein the signal transmission line is periodically connected to a predetermined potential for periods of time when the signals on the transmission line contain extraneous signal components so that only the regular pulse components contained in the original signals are delivered from the transmission line.

A frame synchronization system has false random signals produced by output clock signals of a voltage controlled oscillator and clock signals produced by shifting the output clock signals by .pi./2 and input signals correlated by correlators. The voltage corresponding to the phase difference is applied to an input of the voltage controlled oscillator. Correlators correlate the output clock signals of the voltage controlled oscillator. A level detection circuit detects a specific level of positive polarity of the output of the correlators. The system pulls a frame into synchronization at a true stable point by feeding to an input of the voltage controlled oscillator the voltage corresponding to the phase difference obtained from the correlation between the clock signals shifted by .pi./2 and the input signals when a specific level is detected in the level detection circuit.

The present invention comprises a communication system including a number of independently operating equipment modules in which the operations of these modules are referenced to a common external signal and thereby phase synchronized in order to reduce intra-system interference. The system includes a number of phase lock loop type processing circuits one of which is associated with each equipment module for tracking the external reference signal and generating a base reference for use by module with which each processing circuit is associated. The system takes advantage of the inherent capabilities of phase lock loop circuits to provide a base reference for each equipment module which is characterized by a frequency spectrum having a reduced level of spurious signals and noise. The preferred embodiment includes components for automatically switching between internally and externally generated reference signals and for automatically converting an external reference signal to a standard frequency.