A system for controlling the transfer of pages between a large disc memory and a much smaller core memory in response to requests for the transfer of pages from the disc memory to the core memory, including a first plurality of control words, which define an In-Core List. Each of these control words is associated with a different core page. The word's fields are used to designate various information related to the disc page located in the core page associated with the word, as well as the availability of the core page to have a disc page transferred thereto. The system includes circuitry to form a Paging Queue comprising of other control words. Each word in the Paging Queue includes all the information necessary to define which core page should be emptied of which disc page located therein, to make room for a new disc page which is requested, and/or the number of a new disc page and the core page into which it is to be transferred. The transferring of pages between the memories is independent of the order in which page requests are received. The accessibility of the core memory is dynamically variable.
A programmable control unit for disk memory and controller comprising a microprocessor (MPU), random access memory (RAM) used as a buffer to cache disk resident data used by a data processing system (DPS), and a configurable data path (CDP) which couples the DPS to the disk controller. The (MPU) is programmed to provide the DPS rapid access to disk resident data by so controlling the CDP as to maintain a memory cache of disk resident data in the RAM. Data is cached under either directed control via an application level task or operator console directive, or under dynamic control through which a predetermined number of successive blocks of data are read from the disk and stored in the RAM each time any one block is addressed, and once the RAM is full, by discarding from the RAM a block of data which the immediate history has shown is least useful.
A data processing system using a high speed buffer storage to interface main storage with a central processing unit. Algorithms for the purpose of prefetching the next sequential line from main storage to the high speed buffer and for replacement of existing lines in the high speed buffer may be dynamically modified relative to the type of program being executed by the use of a system console unit.
A hierarchial memory/storage system in which the data is transferred between a high speed local storage, responsive to the processing unit of the computer, and a plurality of higher levels of larger low speed storage wherein data available to the central processing unit is shifted between the various levels of the hierarchial system in a highly efficient manner. In operation, the system in responding to the central processing unit for making available data in the high speed lowest hierarchial level, will seek out the instant lowest buffer memory/storage level containing the required information, form a path of expendable blocks or page frames in the various buffer levels from the adjacent lower level down to the H.sub.1 level, shift any updated information in the path of expendable pages to the off-the-path pages at appropriate higher levels utilizing the successively lengthened cleared upper path for forward and rearward transfer of blocks or pages within the memory system, and subsequently, when the complete clear path of expendable blocks or page frames is formed, transfer and filter the called-for data segments through the path to the level of the hierarchial memory responsive to the processing unit of the computer.
Storage registers equal in number to the number of addressable locations in an associated store of items, such as a content addressable memory, each of which holds one memory address. When a location in the store is accessed, its address is entered into the first address register and the content of all the registers up to but not including the one containing the accessed address are moved to the next register so that the registers contain a list of the order in which locations are accessed, the last register containing the address of the least recently used location.
A unique control circuit that maintains the addressability to an invalidated page frame until execution is completed for all current instructions in all CPUs of a multiprocessing system which uses demand-paging and virtual addressing. A support method is also disclosed which provides an asynchronous sequence of operations for each CPU in the multiprocessing system to maintain the page in the invalidated page frame available to all CPUs and until their current instruction execution is completed. The last CPU to complete its execution moves the page, if modified, out of the page frame.
