An address generator for an M-interleaved memory for accessing row or column elements of a matrix stored in a skewed matrix pattern includes an apparatus for circularly shifting the addresses for the i.sup.th row of a matrix by s(i-1) positions so that both row and column elements of the matrix can be accessed at the same access rate. In other words, apparatus is provided for circularly generating the sequences of appropriate memory addresses for the desired row or column elements so that either the row or column elements can be accessed at the memory system's maximum access rate. The apparatus includes a base register having an input connected to a first adder which adds an input value A to the contents in the base register for storing the output of the adder as a pointer to the beginning of the current row of the matrix in the memory to be accessed. The apparatus further includes an index register having an input connected to an adder for adding an input value B to the contents of the index register and that sum is conditionally added in a third adder to an input value C which sum is then stored in the index register for indicating which column element in the matrix is to be accessed. The apparatus further includes an adder having inputs connected to the base register and the index register for generating the skewed matrix address to be accessed. The resulting apparatus enables both row and column elements of the matrix to be accessed at substantially the same rate.

A memory management device includes circuits having a DCh base activate in a set of N circular commands, h successive commands among the set of commands. A device DCh activates h columns among K: S.sub.0, . . . , S.sub.K-1. A device DC2 activates two line sections among 2L: S'.sub.0, S".sub.0, . . . , S'.sub.L-1, S".sub.L-1. The device DC2 is dependent upon a condition C.sub.d which indicates if a limit d is exceeded by the activated columns, in which case the activation goes from S'.sub.i and S".sub.i and S'.sub.i+1, or else from S".sub.i and S'.sub.i+1 to S'.sub.i+1 and S".sub.i+1 and so on. Selection of groups of memory cells in a matrix-organized field is by high and low addresses transmitted to the devices DC2 and DCh by means of buses B.sub.L and B.sub.K.

A method of operating optical pattern recognition apparatus which relies upon second opinions in which stored offset coordinates match one another within a predetermined tolerance to avoid unnecessarily high numbers of rejects, undesirable levels of risk in terms of pattern misalignments, or excessive cycle times in terms of unnecessary looping through different grey level thresholds.

A data processing arrangement is operative to combine data representing different kinds of information from disparate sources. The data is stored under assigned addresses having a mutually compatible co-ordinate format, and is processed using those addresses. Relevant portions of data from a very large amount of information can be readily extracted in this way, and combined with other data which is related by virtue of a common address. The arrangement is applicable to flight management of an aircraft.

A system and method for controlling operation of a plurality of elements in an automated process, such as a production process, and indicating error conditions as they occur. Each unique set of input and output conditions of the various system elements defines a unique logic state or zone. Thus, there are defined a multiplicity of valid system logic states or zones, each having a unique input/output image. A predetermined sequence of zones, productive zones representing designed machine operations, is stored in a zone table. All zones not explicitly defined in the zone table are automatically treated as error zones. A zone engine automatically cycles to observe any change in input/output image. Any change in inputs from the various system elements automatically transfer action to the unique zone associated with such inputs, resulting in corresponding changes in control outputs to the system elements and/or display an error message as appropriate.