or
Bookmark and Share
LATERAL TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME
   
Document Number
US Patent 3651565
Issued Date
March 28, 1972
Link
Inventors
Map
Abstract
A process for making a lateral PNP semiconductor device having a .beta. within the range of 5 to 500 wherein, during a heating stage, a metallic layer is left covering the surface of the wafer above substantially all of the base region separating the emitter and collector regions. The resultant effect is to cause a marked increase in the current gain of the transistor thus constructed over those similar devices manufactured in accordance with prior art processes.
Drawing
LATERAL TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME - US Patent 3651565 Drawing
Drawing from US Patent 3651565
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
6
Comments:
no comments yet
Owner
Published
March 28, 1972
Application Number
04/758,340
Filed
September 9, 1968
US Classification
438/335   148/DIG.135 257/593 438/369
Int'l Classification
H01L   23/48   (20060101)   H01L   29/66   (20060101)   H01L   27/00   (20060101)   H01L   29/00   (20060101)   H01L   29/73   (20060101)   H01L   21/00   (20060101)   H01L   23/485   (20060101)  
Assistant Examiner
USPTO Field of Search
29/589   29/590   29/591   29/578   29/571   29/576   317/235   317/21.1   317/46   317/40.1   317/40.12  
Related Patents
4985367 - Method of manufacturing a lateral transistor - Owned by Kabushiki Kaisha Toshiba (Kawasaki,JP)

A method of manufacturing a lateral transistor which comprises the steps of forming N type semiconductor silicon layer on P type semiconductor substrate, depositing base region on part of the semiconductor silicon layer, forming field oxide layer bearing an opening on the base region, forming thin insulation layer on that part of the semiconductor body which is exposed by the opening, forming an annular pattern on the thin insulation layer, implanting a P type impurity in the base region, thereby providing an emitter region and collector region in the self-aligned fashion with respect to the annular pattern, retaining the annular pattern, and depositing insulation layer on the resultant structure, boring an emitter contact hole having a smaller diameter than the outer diameter of the annular pattern, and forming emitter contact hole in the self-aligned fashion with respect to the annular pattern, and forming emitter electrode in contact with the emitter region through the contact hole.

4361846 - Lateral type semiconductor devices with enlarged, large radii collector contact regions for high reverse voltage - Owned by Hitachi, Ltd. (Tokyo,JP)

Lateral type semiconductor devices are provided which can withstand a high applied reverse voltage and can be effectively employed in semiconductor integrated circuits with an enhanced integration density. These lateral type semiconductor devices include therein an island region formed in a semiconductor supporting region and a diffusion region formed in the island region. The radius of curvature at the pn junction surface of the diffusion region is selected to be at least 1.5 times larger than the depth of the diffusion region. The diffusion region includes electrode mounting portions of large area and the remaining portions having the form of a fine line.

Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us