A communications exchange for automatically interconnecting subscriber lines and trunks employs a switching network operable to establish a large number of possible message transmission paths between subscriber terminators and trunk terminators; multiple computers are operable simultaneously upon network transmitted message processing data to similarly process the data and produce output signals; and communication of data between the switching network and computers is established through a system controller operable to determine which computers shall be preferred as communicating valid data and which of the preferred computers shall be used as a sole survivor to transmit valid processing data to the network.
A method for collecting data from electronic voting units standing by to receive enabling commands, comprising: sending in parallel a vote opening/control command from a central logic unit to a plurality of peripheral logic units by way of first connection elements and to voting units by way of second connection elements; storing the vote in the voting unit if the vote opening/control command is a vote opening command; setting the voting units to the stored vote sending mode; sending in succession, from each individual peripheral logic unit, a vote collection command; sending to the peripheral logic units a vote signal from each one of the voting units in a preset time interval; and transmitting the votes collected by the peripheral logic units to the central logic unit and to a computer.
The interface disclosed herein is capable of operating in the TMR/S (triple modular redundancy with sparing), the comparison, and the simplex modes. The interface controls the interconnection between m.sub.1 , . . . , m.sub.n identical sending modules and M.sub.1 , . . . , M.sub.n identical receiving modules. To this end, there are provided 1, . . . , n control registers which comprise 1, . . . , n bits and an (n+1).sup.th control register which comprises a single bit R.sub.S. The register bits are employed to provide n.sup.2 forcing functions for the outputs d.sub.1, . . . , d.sub.n of the sending modules which are represented by the following logical equation: ##SPC1## Wherein j is the bit number, 1, . . . , n, i is the register number 1,..., n, the symbol .vertline. .vertline..sub.n signifies modulo n and V represents the OR function. The n.sup.2 forcing functions are respectively applied in sets of n viz., f.sub.1 i, f.sub.2 i, . . . , f.sub.n i i = 1,2, . . . , n to (1, . . . , n).sup.th threshold function circuits, each of the latter circuits producing a "1" output when .gtoreq.2 of the inputs thereto are "1", the outputs of the (1, . . . , n).sup.th threshold function circuits being applied to the M.sub.1, . . . , M.sub.n).sup.th receiving modules, respectively. From the register settings and the sending module outputs, there are generated pairs represented by the logical equation C.sub.ij = (d.sub.i V R.sub.ij V R.sub.ji V R.sub.S, d.sub.j R.sub.ij R.sub.ji V R.sub.s) for j = i+1 (i=1, 3, 5, . . . , n-1) C.sub.ij = (d.sub.i V R.sub.ij V R.sub.ji, d.sub.j R.sub.ij R.sub.ji) for j.noteq.i+i Wherein the ij pair in the first equation can take the values of 13, 14, . . . , 1n, 24n, . . . , (n-2)n. From the pairs, (ij), there are generated register triggers having the following equations: A.sub.1 = .sym./C.sub.12 .LAMBDA..sub.M C.sub.13 .LAMBDA..sub.M C.sub.14 .LAMBDA..sub.M . . . .LAMBDA..sub.M C.sub.1n A.sub.2 = .sym./C.sub.21 .LAMBDA..sub.M C.sub.23 .LAMBDA..sub.M C.sub.24 .LAMBDA..sub.M . . . .LAMBDA..sub.M C.sub.2n A.sub.n = .sym./C.sub.1n .LAMBDA..sub.M C.sub.2n .LAMBDA..sub.M C.sub.3n .LAMBDA..sub.M . . . .LAMBDA..sub.M C.sub.(n.sub.-1)n Wherein the symbol .LAMBDA..sub.M represents the morphic AND function called the RCCO in U.S. Pat. No. 3,559,167, the symbol .sym. signifies the exclusive OR function on the pair of lines that are outputs of the morphic AND. The (A.sub.1, . . . ,A.sub.n).sup.th triggers are applied to the (1, . . . , n).sup.th bits of the registers respectively, to switch the bits to the opposites of their initial binary states whereby, upon the generation of a register trigger A.sub.j and the consequent switching of register bits R.sub.1j, . . . , R.sub.nj to their opposite binary states, sending module m.sub.j is disconnected from operation. To operate the interface in the TMR/S mode, initially all of the bits of the (1, . . . , n).sup.th registers are initially set to the 1 state and the bit of the (n+ 1).sup. th register is set to the 0 state. To operate the interface in the comparison mode, all the bits bearing the same numerical designation as the sending module which are to be compared in the registers bearing the same numerical designations as the sending modules which are to be compared are initially set to the 1 state with all of the other bits set to the 0 state. To operate in the simplex mode, all of the bits in the (1, . . . ,n).sup.th registers except those bearing the same numerical designation as that borne by the register in which they are contained are set to the 0 state, the excepted bits being set to the 1 state. Also, in the simplex mode of operation, the bit of the n+1.sup.th register is set to the 1 state.
A facility called "Gateway" is used to interconnect a plurality of independently controlled communication networks so that logical units (LUs) in the networks can communicate with one another without any changes to the network. The gateway includes a programmable device or devices which establish and monitor cross network sessions and for each formatted message, on the session, the programmable device changes the contents on the request unit (RU) and/or the transmission header (TH) fields so that data is delivered to a target LU. The changes include address translation within the TH field, and/or address and name translation within the RU field.
In a data processing system comprising a plurality of systems each including a plurality of console type typewriters for establishing communications pertaining to data processing operations between an operator and the system, the communication information which is entered into and derived from a central processing unit in each system by the console type typewriter is stored in a character buffer unit corresponding to the console type typewriter in a monitor transfer control unit, and a buffer scanning unit scans the character buffers to transfer the contents therein into a statistical analyzer or processing unit so that communication information may be automatically analyzed and summarized to obtain the data per day or month required for determining whether or not the data processing system has been effectively operated.
A sulfur dioxide containing gas is purified by successive contact with an ammonia solution and then a dilute ammonium sulfite solution; the latter solution is regenerated by electrodialysis while the ammonia solution, after SO.sub.2 absorption, is vaporized in order to recover ammonia and sulfur dioxide.
