A field effect semiconductor device including a plurality of field effect semiconductor elements formed on a common substrate and a compensating circuit for controlling the threshold voltage of said transistors by comparing the threshold voltage of one transistor to a reference voltage and generating a backward bias control voltage across a PN-junction of the one transistor between the source thereof, which is connected to the source of at least one of the other transistors, and the common substrate.
A capacitance multiplier circuit having first and second terminals adapted for use in integrated circuits. An NPN transistor has its emitter connected to the second terminal, its base connected to one electrode of a capacitor and its collector connected to the other electrode of the capacitor and also to the first terminal. Increasing the voltage of the first terminal causes a charging current to flow in the capacitor and into the base of the transistor. The capacitor charging current is multiplied by the current gain of the transistor. The apparent capacitance between the first and second terminals is equal to the capacitance of the capacitor multiplied by the current gain of the transistor.
A number of compensating circuits each of which provides an output voltage which differs from an applied input voltage by one or more IGFET threshold voltages. Each circuit typically includes a main IGFET, a load IGFET and one or more bias control IGFETS in the gate branch of either the active or load transistor. Specific compensating circuits adapted for use in the regenerator of a charge transfer device and in a constant current generator are disclosed.
Two field-effect transistors interconnected in such a way that the output voltage produced by the first, which is a function of its voltage threshold, controls the conductivity of the second. One transistor may be reverse biased source-to-substrate to maintain its threshold voltage higher than that of the other. A small change in voltage level may be detected by this circuit by causing that change concurrently to reduce the source-to-substrate reverse bias of the first transistor and to reverse bias the source-to-substrate of the second transistor.
An on chip field effect transistor circuit is disclosed for electrically compensating for variations in process parameters which have occurred during the course of fabrication of the integrated circuit chip as well as variations in environmental parameters such as supply voltages and temperature. The compensation is performed by utilizing three field effect transistor devices on the integrated semiconductor chip as a sensor to detect variations in the characteristics of the devices due to deviations in the process parameters during fabrication thereof. The sensing field effect transistors operate in a circuit to adjust the gate potential of FET load devices in those functional circuits on the integrated circuit chip whose sensitivity to the variations in the process parameters is critical to the operation of the circuit as a whole.
A transistor (Q3, Q4) is configured to act as a current source. Of importance, the current provided by the current source has a process-selectable temperature dependence. By introducing ions into the transistor gate insulation (14, 20) the current provided by the current source can be either temperature independent, inversely related to temperature, or directly related to temperature, as desired.
