A floating gate transistor comprising a floating silicon or metal gate in a field effect transistor which is particularly useful in a read-only memory is disclosed. The gate which is surrounded by an insulative material such as SiO.sub.2 is charged by transferring charged particles (i.e., electrons) across the insulation from the substrate during an avalanche (breakdown) condition in the source or drain junctions of the transistor.
Disclosed is a memory cell incorporating the major advantages of a read only storage (ROS) and having the flexibility of on-chip personalization after processing. In a memory matrix having orthogonally arranged bit lines and word lines with memory cells located at the cross points, each of the disclosed memory cells constructed in accordance with BIFET technology includes a floating gate avalanche breakdown MOS transistor (FAMOS) coupled to a bipolar transistor. The residual charge on the floating gate FAMOS transistor determines the logical state of the read mostly memory cell.
An object of the present invention is to ease the dielectric strength requirements for transistors forming power supply circuits or the like. A nonvolatile semiconductor memory of the present invention includes a plurality of memory cells, each of which is composed of a floating gate, a control gate, a drain, and a source, and a negative voltage generating means whose generated negative voltage is applied to the control gate for drawing a charge stored in the floating gate into a channel or the source when stored data is erased electrically. The nonvolatile memory of the present invention further includes positive erasure voltage generating means, and a positive voltage higher than a conventional supply voltage generated by the positive erasure voltage generating means is applied to the channel or the source.
A dynamic RAM comprises first and second memory cell arrays respectively outputting holding data to corresponding bit lines when selected, sense amplifier means having amplifying MOS transistor for amplifying output of the bit lines of the first and second memory cell arrays, first and second transfer gate means respectively providing corresponding to the first and second memory cell arrays and controlling establishing and blocking connection between corresponding memory cell array and the sense amplifier means, first and second driver means respective provided corresponding to the first and second transfer gate means and generating gate control voltages for corresponding transfer gate means. Each of the first and second driver means comprises intermediate voltage setting means operable at a first voltage and a second voltage different from the first voltage, having the same conductive type with the amplifying MOS transistor, and at a stand-by state, for setting the gate control voltage of the transfer gate means at a third voltage which is level shifted from the first voltage in an extent corresponding to a threshold voltage of the MOS transistor, and selection voltage setting means for setting the gate control voltage of the transfer gate means corresponding to the memory cell array of the selected side at the first voltage and setting the gate control voltage of the transfer gate means corresponding to the memory cell array of the non-selected side at the second voltage, upon selection of the memory cell arrays.
In an integrated circuit, a semiconductor body having a surface, spaced semiconductor circuits formed in the body, intercoupling means formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.
A groove is formed in a semiconductor layer, and a source region is formed at a part of the groove within the semiconductor layer. A control gate is buried via a first insulating layer within the groove. A floating gate is formed via a second insulating layer on the control gate. The floating gate extends over the first insulating layer. A drain region is formed within the semiconductor layer apart from the groove.
