An apparatus for extracting and generating a clock pulse train from a pulse coded data train. The apparatus includes a filter circuit for receiving the pulse coded data train. A first set-reset flip-flop is provided for receiving the signals from the pulse coded train. Coupled to the output of the first flip-flop is a means for generating a triggering pulse responsive to the occurrence of data within the train. A pulse gate activated by said triggering pulse for causing the data from said pulse coded data train to be stored in a second flip-flop. A clock pulse generating means is coupled between the outputs of the first and second flip-flops for generating a continuous stream of clock pulses which are synchronized with the incoming pulse coded data train.

An AFC (auto frequency control) loop circuit is provided to generate first synchronizing pulses synchronized with horizontal synchronizing signal separated from a composite synchronizing signal. A first synchronous flip-flop connected to receive this synchronizing pulse as clock pulse and a vertical synchronizing signal separated from the composite synchronizing signal. The output of the first flip-flop is applied to an input of a second synchronous flip-flop which is connected to receive the first synchronizing pulses as clock pulses. Second synchronizing pulses are obtained by a logical product operator circuit to perform the logical product operation between an inverted output of the first flip-flop and an output of the second flip-flop. The second synchronizing pulse is produced taking the trailing edge of the vertical synchronizing signal separated from the composite synchronizing signal as a reference and thus functions as a stable vertical synchronizing signal.

This invention involves a circuit capable of phase locking onto a data input signal for the separation of the clocking and data segments of the signal.

The method consists of using the recovered bit rate signal to define a time window which overlaps the beginning, but not the end of each jitter range in the version of the digital train intended for use by the bit rate recovery circuit. Those transitions in said version of the digital train which occur during said window are then delayed by a fixed delay of duration less than the maximum peak-to-peak amplitude of the jitter. Other transitions are not delayed. The apparatus shown is intended to operate with a binary version I of the digital train and with a recovered bit rate signal H which is symmetrical and rectangular in shape with a first one its levels defining a time window which extends over the second half of each period in the digital train. The apparatus is essentially constituted by a pulse generator (10) which transforms the transitions in the binary version I of the digital train into pulses of duration .tau. equal to one-half of the maximum peak-to-peak amplitude of the jitter, a first D-type register (11) delaying transitions in the recovered bit rate signal (8) so that they lie outside the pulses generated by the pulse generator (10), and a second D-type register (12) which delays transitions in the binary version I to lie outside the periods when the recovered bit rate signal having possibly delayed transitions (J) is at its first level. The apparatus is entirely constituted by logic circuits and is easy to integrate.

A filtering technique for removing noise and enhancing the waveform shape of an information signal train. An incoming signal is subjected to a two bit interval delay. The delayed signal is separately summed with and multiplied by the undelayed signal. The resulting sum and product signals are multiplied together and the resulting product signal is summed with the incoming signal delayed by one bit interval. The resulting sum is passed through a low pass filter and used to drive a limit amplifier to produce the filtered output signal.