A data processing system in which the operating logic thereof is arranged to provide for an overlapping of the access, or "fetch" operations such that access to a second memory module can be obtained by a processor unit before a data transfer has been completed with respect to a first memory module and read-out of the second memory module can process during the rewrite cycle of the first module to reduce the overall processing time. Such operation is made even more effective by arranging the system to utilize memory interleaving techniques. Further, the system of the invention can provide for multiprocessor operation with a single memory system by the use of appropriate time-sharing techniques wherein processors can be operated in time-phased pairs, suitable multiprocessor control logic being arranged to provide for preselected priority allocations among the multiple processors to permit the most effective management of the multiprocessor system.

An instruction decoder, for a variable byte processor, is capable of making the variable byte processor operate at a high processing speed and high byte efficiency. The instruction decoder includes an instruction register which stores instructions applied to an internal data bus, a first instruction decoding unit which provides a consecutive instruction execution mode signal specifying the repetitive execution of the instruction read from the instruction register for different operands stored at different addresses, a consecutive instruction execution cycle monitoring unit which counts the number of execution cycles of the instruction and provides a signal indicating the completion of the repetitive execution of the instruction, register/counters which count the number of execution cycles and provide operands of different addresses every time an execution cycle is completed, a second instruction decoding unit which sequentially specifies data stored at different operand addresses in response to the output signals of the register/counters, and a gate which inhibits the instruction register from reading a new instruction until the instruction is repeated by the specified number of execution cycles.

A micro program system is disclosed which employs two levels of subinstruction sets. The first level of subinstructions, or micro instructions, is implemented by a second level of control instructions that can be stored in a processor read-only memory. The respective micro instructions are made up of varying numbers of syllables according to the function of the particular micro instructions. The various types of micro instruction syllables are stored in a micro instruction memory to be fetched therefrom in sequence in accordance with the requirements of a particular micro instruction or subject instruction. In this manner, a variety of micro instructions can be created by selecting a plurality of different syllables from the micro instruction memory. A different micro instruction syllable is provided to specify each combination of the function to be performed and the source and destination registers to be used with the particular buses in the processor.

An operation control system for a micro-computer comprises a control unit and a register unit. A micro instruction stored in a read only memory of the control unit is fetched, a one word instruction is divided into six time stages and the divided instructions are transmitted to the register unit in a time-multiplexed format with each stage being a fundamental time unit, while the register unit decodes the micro instructions of the fundamental units fed thereto and executes the micro instructions of the fundamental units in a manner to overlap in time.

Disclosed is a digital data processing system comprised of a main store, a storage control including a buffer store, a channel unit, an instruction unit, an execution unit and a console. The system is controlled by instructions which operate upon data to carry out desired data manipulations. Groups of instructions form a program where the program normally has its instructions sequentially executed, one at a time, to carry out a complete data manipulation. The instruction unit concurrently processes a plurality of instructions in an instruction pipeline which functions with a two-cycle, time-offset between instructions. That offset is an integral multiple of the cycle time of the functional units which execute instructions and is matched to instructions which use two storage accesses per execution where each access to storage requires one cycle.