An electronic memory cell consists of a bistable circuit and three access paths. Two of the access paths are used to control the state of the bistable, one of these paths being used to set the bistable, to one of its two stable states and the other of these access paths to set the bistable to the other stable state. A low impedance path is provided between one of these two access paths and the third access path in dependence on the state of the bistable to permit read-out of the memory cell.
A multivibrator utilizing two split inverter pairs of MOSFETS and requiring a supply voltage less than the sum of the threshold voltages of the complementary P-N channel devices. The transconductances of each pair are balanced to provide temperature compensation. MOS capacitors can also be utilized. Good frequency stability and low current drain are inherent in the design.
A memory cell as required for use in the building of integrated memories, which contains bistable trigger stages formed by two transistors, with a high operational reliability, a low power consumption and an access time of less than 0.01 microseconds for a store of 64 elements, is provided. To this end, low-consumption field-effect transistors are chosen, obtained by the ion implantation of an N-type channel, in order, in each cell, to form, in addition to the two transistors of the trigger stage, a pair of transistors connected as amplifier-followers. The selection of a cell is effected by raising the potential on the word line connected to the sources of the transistors of the trigger stage.
A contents addressable memory comprising an array of contents addressable memory cells arranged in rows and columns, each row of the array having a respective case between address bit values of a data word or words to be retrieved from the memory and bit values held by the cells of the respective row, and a chain of cells associated one with each match line to indicate which, if there are more than one, of the match lines indicating a match is of the highest priority.
An integrated semiconductor memory with storage elements in a circuit employing a flip flop with field-effect selective transistors and with an arrangement based on the two or multiple coincidence principle, with corresponding control lines.
A memory system has a data storage element connected by a first memory read device to a first memory output line and by a second memory read device to a second memory output line. A first and a second decoder are connected to the first and second memory read devices, respectively, to read-out data stored in the storage element in response to read address signals applied to the first and second decoders. A "write" operation is effected on the storage element by a write-in device connected between a data input line and the storage element and energized by a third decoder arranged to respond to a write address signal.
