There is described an apparatus for monitoring the contents of any selected location in the main memory of a computer. The contents of an addressed location in memory is read out periodically and compared with the prior contents of the same memory location. On sensing a change in the contents of the memory location, operation of the computer is halted.
A small size digital computer system is designed so that a hardware memory violation protect subsystem may be added to the computer system as a hardware option. The memory protect subsystem includes hardware which may operate in parallel with the digital computer system memory subsystem and which monitors each attempt to alter data within the memory subsystem. Any attempt to alter data within a protected region may be defeated. Following such an attempt, program execution is interrupted and program control is transferred to the computer system executive software. The computer system is also designed so that it may either modify or prevent the execution of certain instructions at times when the memory protect subsystem is in operation so as to defeat all attempts on the part of any software entity to destroy the integrity of the operating system.
The invention provides arrangements for diagnosing faulty equipment using background job diagnostic software running in the on-line PP250 system. Each processor is provided with a diagnostic interface which is connectable to a processor-store bus, either directly or by way of a multiplexor, and which is addressable as part of the PP250 memory complex. Each diagnostic interface provides facilities for (i) forcing data patterns into the microbits and the data area (highway HO), (ii) monitoring important points in the processor equipment such as highway HO, the data-out register, the microbits and (iii) various basic functions relative to the stopping of the micro-program. The diagnostic interface printed circuit boards are normally removed and inserted only when a processor is to be diagnostically exercised.
A data processing system includes a memory in which information is stored in segments and at least one processor unit arranged to co-operate with the memory and provided with at least one so-called capability register arranged to store a segment descriptor which includes information indicative of the base and limit addresses of a particular memory segment and is used in all memory access operations relevant to the particular memory segment and the processor unit includes a program interrupt arrangement having interrupt actuating means which when activated causes the processing of the current program to be suspended and the processing of an interrupt handling program to be commenced. The processor unit is provided with capability register restoration arrangements operative to load at least part of the capability register with a discrete characteristic code and discrete characteristic code detection means arranged to monitor the information content of each capability register as it is used and to activate the interrupt actuating means upon detection of the discrete characteristic code.
A data processing technique is disclosed which permits a plurality of users of a data processing system to share data in a data store, providing independent and asynchronous access to the data for subsequent processing by either user. The sharing of small data items is accomplished without requiring the use of interlocks to prevent one user from obtaining access to the shared data item while the other is processing the data for subsequent replacement in the shared data store. In addition, sharing of data items of sufficient size permit the user to build up controls for safe and efficient sharing of data items of any size.
This invention provides an improved data processing apparatus of the kind having at least one data processing unit, and a central memory unit controlled by an associated instructions register. With the object of reducing the processing time the apparatus includes a sentinel memory which receives a given programmed instruction and a comparator which compares continuously the contents of the instructions register of the central memory with the contents of a sentinel memory to provide a control signal for the control unit of the apparatus when the contents of the instructions register and the sentinel memory are identical.