A machine for emulating the results of multi-level storage hierarchies by providing an associative storage directory for each level other than main storage. Address sequences to drive the directories are derived from a single level digital computer by recording sequences on tape or by dynamically monitoring computer operation. Individual addresses are skewed an appropriate number of bits depending upon the block size and the number of classes being emulated at any given level, so that those bits of the monitored address indicating segment name are presented to the directory for comparison with its contents in the appropriate class. Means are provided for transposing the segment and class names at higher levels to segment and class names at lower levels. Counting means are provided to record hits, misses and pushes at various levels in order to provide data for calculating average access times for the particular multi-level storage hierarchy being emulated.

The method serves to operate an address translation device for translating a virtual address of a virtual address space comprising a plurality of pages into a physical address of a physical address space comprising a plurality of pages, with the use of a translation lookaside buffer and a page table. The address translation is performed in the following manner: the translation lookaside buffer is indexed to an index by the routing code associated with the virtual address or by a mapping of the routing code associated with the virtual address, or it is indexed to an index by a mapping of the routing code associated with the virtual address and the first address portion of the virtual address. In case of a TLB hit, a page table parsing is executed using only the virtual address. The routing code used to index the TLB is not included in the page table parsing.

A memory access apparatus in which a data memory has a plurality of data storing areas is accessed by a CPU in accordance with a sequential access method. A window latch and an adder are provided between the memory and CPU. Addresses stored in the window latch and addresses issued by the CPU are added together to create a memory access address. The window latch is so set that a data storing area within the data memory corresponding to an inputted spelling of a word is accessible by the CPU.

In this apparatus for dynamically translating virtual memory addresses to real memory addresses, a master system page table maintained in a memory associates real memory addresses with their corresponding system virtual memory addresses. This table is organized with each virtual memory address stored in it at an index location which is a smaller value formed as a predetermined function of the virtual memory address value. The translator forms the index from the virtual memory address according to the function, enters the table with it, and extracts the corresponding real memory address. In a preferred embodiment, every process (i.e., job) may reference any address in any segment of a process virtual address space, and a dedicated mechanism converts such a process virtual address reference to a system virtual memory address, which then is converted to the real memory address.

A data processing system with virtual memory and the ability to vary the program window size for each program to be processed. The system includes at least one processor, a main memory, a secondary storage and a channel to handle data transfer between the secondary storage and main memory. Each processor is provided with means to measure the processing time of the processor and the data transfer time of the channel for transferring either variable segments or fixed pages from the secondary storage to main memory in response to page faults. A program table is provided in the processor to contain names of pages which reside in main memory for the current program, which table implements a page replacement mechanism such that as new pages are transferred to main memory for the current program, the least recently used pages are removed therefrom. Each word location of the program table is provided with a counter or register to record the average time duration between virtual faults for that word location where a virtual fault is that incident which would be an actual fault if the program window size contained only that number of page frames. This in turn allows for variation of the current program window size to increase or decrease the number of page faults occurring for the current program in accordance with the ratio of the computation time to data transfer time being significantly greater than or less than one respectively.