In semiconductor memory cells of the type including flip flop circuits in each cell and two sense output lines for determining the binary bits stored in the cell, an attempt to read data stored in the cell after a previous operation, before the sense lines have been fully restored to their quiescent state can result in the loss of data. This invention provides a means for restoring the sense lines very rapidly after an operation so that loss of data is prevented and the memory may be accessed at a higher frequency.

A speed-up circuit for a bit sense line of an MOS RAM includes a cross-coupled latch circuit having an output coupled to the bit sense line. When partial discharging of the bit sense line is accomplished through the selected storage cell, the latch circuit switches states and completes discharge of the bit sense line much more rapidly than could have been achieved by the action of the selected storage cell alone. A disabling circuit is connected to the gate of a pull-down MOSFET of the latch circuit connected to the output thereof to turn off the pull-down MOSFET during a write cycle or during the write portion of a read-modify-write cycle. The output of the disabling, or turn-off, circuit operates in response to a signal derived from a clock signal and a chip enable signal applied to the MOS RAM. A bootstrap circuit is provided including a bootstrap charging MOSFET having its gate coupled to V.sub.DD, its source coupled to the bootstrap capacitor, and its drain coupled to a clock signal conductor, to provide low-power dissipation and fast rise time.

An associative memory cell includes a storage device having a pair of biasing nodes and a pair of output nodes, a plurality of access lines including a pair of BIT-lines and a TAG-line, and a plurality of gates controlling the accessing of the storage device by the access lines. The latter gates include a pair of sampling gates under the control of the BIT-lines and connecting the output nodes of the storage device to a pair of sampling nodes, and a pair of TAG-gates under the control of the sampling nodes and connecting the TAG-lines to one of the pair of the storage device biasing nodes. The described memory cell further includes READ-control and WRITE-control lines with the associated gates to perform the READ and WRITE functions. The pair of BIT-lines, the WRITE-control line and the READ-control line are all connected to the gate terminals of their respective gates, thereby making the device easier to drive, isolating the memory cell from the BIT-line buses, and improving reliability and speed.

A self-refresh MOS RAM cell uses a resistor element made by an ion implant step compatable with a self-aligned N-channel silicon-gate process. The resistor element is beneath the field oxide in the finished device, although the implant step is prior to formation of the thick oxide. The cell employs two transistors and a gated capacitor, connected in a manner such that a stored "1" switches the implanted resistor to a high impedance state, while a stored "0" maintains the resistor in a relatively low resistance state.

A translator is organized to include at least a pair of content addressable memories (CAMs), each for storing a different portion of the total number of bits of each of the words to be translated. The outputs from each CAM are logically combined within a multiple input random access memory (RAM). Both CAMs are interrogated simultaneously and deliver the results of comparing the word portions of an input word and the CAM contents to the RAM in substantially less time then required for a single CAM memory. The results are logically combined with in the RAM which, in response to a match condition, delivers the results of the translation as an output.