A loop system couples a CPU channel to bulk storage devices via a loop controller and device adapter. The loop system is characterized by equal fixed-length, multi-byte frames, each frame of which being assignable to only one terminal at a time. The system is further characterized by having a fixed loop delay greatly exceeding the frame duration by virtue of the high data rate. Dynamically variable frame assignment occurs when the primary terminal generates an unassigned empty frame in response to each assigned full (read) frame from a secondary terminal. The primary further generates an assigned full (write) frame upon receipt of each service (write) request frame from a secondary terminal. Lastly, the primary can send access command frames for each received unassigned empty frame or any other frame that does not imply a demand for bandwidth by the secondary. Relatedly, each secondary terminal can optionally write over a frame assigned to it or should it not have a message or data to send to the primary, change the "full" frame to "empty", or to seize an unassigned empty frame as it passes by on the loop. The combination of secondary terminal frame reuse with that of the primary tends to distribute frame availability on a more nearly uniform basis.

A digital switching arrangement having equipment interconnected to provide multiple fault tolerances in the digital switching of PCM (Pulse Code Modulated) data over time division multiplex lines. The digital switching arrangement includes a set of peripheral units interconnected via a switching network. The set of peripherals includes input/output facilities such as digital trunks, analog trunks, and subscriber lines and also includes control processors and related common control equipment. Peripheral units are connected to the switching network over digital links. The digital links carry multiplexed PCM data and serve as the exclusive interface between the outside world and the switching network. The multiplexed content of the digital links is further interleaved on superhighways within the switching network in such a manner as to uniformly distribute traffic as well as increase system reliability. Time-space-time switching is performed between incoming and outgoing superhighways over a modular time-space-time switch.

A read-out signal generator supplies read-out signals through a read-out bus bar to sources of first data signals and buffer memories storing second data signals produced by accompanying central processing units (CPU's) to make the read-out bus bar transmit also the first and second data signals in timed relation to the read-out signals. A coupling device supplies read-in signals with reference to the read-out signals and transfers the first and second data signals from the read-out bus bar to a read-in bus bar, which supplies the transferred data signals to the CPU's in predetermined time relation to the read-in signals. The coupling device may either be a mere connection (in which case the read-out signals serve as the read-in signals) or a data bank.

Two asynchronously operating computers which are each controlled by timing periods produced by its own clock are each provided with a pulse treatment circuit which in response to a break signal, interrupts the computer operation during the following timing period. A buffer memory is used in order to transfer information from the first to the second of the computers. Because of the asynchronism there is a risk that the buffer memory becomes either totally occupied or unoccupied. The risk is eliminated by means of an address and break signal generator which generates addresses to control writing and reading of the buffer memory and generates break signals which are sent to the pulse treatment circuit of the first and second computer in order to inhibit information from being sent to the buffer memory when it is full or drawn from the buffer memory when it is empty. The writing and reading addresses are generated by means of a first and a second circulating address counter stepped by the pulse treatment circuit of the first and second computer, respectively. The break signals are generated by means of a comparator connected to the two address counters. In addition the timing periods of the operating cycles have portions during which the computer components work unreliably due to their reaction times i.e., the setting of flip-flops, the ripple in counters, etc. Therefore, a reliability device compares the phases of the timing periods produced by the two computer clocks in order to allow only break signals which are generated owing to the comparison of addresses obtained in period parts during which both address counters are reliable.

A priority arbitration circuit for resolving priority between a plurality of master devices which compete for access to one or more slave devices over a common bus. All master devices share a common Request line and a common Busy line. Priority is passed along serially from one device to another in sequence until all pending requests have been serviced, after which priority reverts to an initial device. The first device to issue a request gains priority. Simultaneous requests are resolved in the order in which the devices are connected in the priority chain. A device having a local request and receiving priority on the priority chain sets the Busy signal to lock out all other devices.