A computer system includes a relatively fast, small, random-access memory, and a large, relatively slow, directly-addressable, random-access memory. An address comparator is receptive to the contents of a real address register and has a first output indicating that the desired word is stored in the fast memory, so that the contents of the real address register can be used to address the fast memory. The address comparator has a second output indicating that the desired word is in the large memory. In this second case, the contents of the real address register is used to directly address the large memory a majority of the time, under control of a random probability device. The remaining small proportion of the time, the computer is interrupted and caused to transfer a page of memory words, including the desired word, from the large memory to the fast memory.
A computer system comprising a storage configuration, including a main store, a buffer store of smaller capacity, and an associated address store. Means are provided so that when a byte or word of a word block is to be written in the main store from a processor or another portion of the system, the buffer store cooperates in the transfer operation, provided the relevant word block is present in the buffer store.
A hierarchial memory/storage system in which the data is transferred between a high speed local storage, responsive to the processing unit of the computer, and a plurality of higher levels of larger low speed storage wherein data available to the central processing unit is shifted between the various levels of the hierarchial system in a highly efficient manner. In operation, the system in responding to the central processing unit for making available data in the high speed lowest hierarchial level, will seek out the instant lowest buffer memory/storage level containing the required information, form a path of expendable blocks or page frames in the various buffer levels from the adjacent lower level down to the H.sub.1 level, shift any updated information in the path of expendable pages to the off-the-path pages at appropriate higher levels utilizing the successively lengthened cleared upper path for forward and rearward transfer of blocks or pages within the memory system, and subsequently, when the complete clear path of expendable blocks or page frames is formed, transfer and filter the called-for data segments through the path to the level of the hierarchial memory responsive to the processing unit of the computer.
This specification describes a virtual memory system comprising a main storage and a smaller high speed buffer. Both main storage and the buffer are real-address oriented. Current virtual-to-real address translations are retained in a Translation Look Aside Table (TLAT) and real addresses of data stored in the buffer are maintained in a buffer directory. The CPU-provided virtual address causes access to the TLAT and to the buffer directory. The virtual address stored in the word accessed from the TLAT is compared to the virtual address from the CPU and the real addresses accessed from the TLAT and the buffer directory are compared to each other. If both comparisons are equal, the data is accessed from the buffer.
A data processing system includes a plurality of system units all connected in common to a system bus. The system units include a central processor (CPU), a memory system and a high speed buffer or cache system. The cache system is word oriented and comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache system. If the cache does not have the information, apparatus in the cache requests the information from main memory, and in addition, the apparatus requests additional information from consecutively higher addresses. If main memory is busy, the cache has apparatus to request fewer words.
This invention relates to a register and more specifically to register control in a data processing system. In general, a number of control registers are theoretically required that is less than the maximum number which can be designated, and only the required number of registers are mounted as hardware. In order to add functions or to provide compatibility with other systems, it is sometimes required to use a register that is not mounted as hardware, or to use the registers mounted as hardware for conflicting purposes. Virtual registers are accordingly provided for at address locations in the memory of the processing system. However, if only the registers to be added are thusly provided for in the memory, the instructions must be executed by distinguishing between register access and memory access, in accordance with register number, etc. Thus, this invention provides a number of virtual registers for instance equal to the number that can be designated. The controls are thereby simplified in accordance with the kind of instruction to be performed. Namely, when an instruction is the LOAD instruction, the same content is loaded into both real an virtual registers from a respective address of the memory, and when it is the STORE instruction, the content from a respective virtual register is stored into the respective address of the memory.
