An analog memory capable of write-in at a relatively low rate and independent, nondestructive read-out at a relatively high rate. A single write-in and read-out address logic is provided for as memory units are desired. Each memory unit includes a matrix of sample and hold microcircuits, each having an external storage capacitor, an isolation amplifier and independent input and output analog switching in response to vertical and horizontal write-in and read-out addressing.
A multiple input switching system includes an input isolation device, such as a transformer, in the input circuit. Switching devices are provided for sequentially connecting the several input circuits to a time-shared amplifier. The switching devices are actuated at a predetermined rate with a predetermined closed-time for each closure. Further switching devices are provided for transferring the data from each of the input circuits to a corresponding memory device. These further switching devices are operated synchronously with the first-mentioned switching devices but with a shorter close-time. The data values in the several memory devices may be selectively scanned asynchronously. Between each actuation of the input switching devices, additional switches are actuated which (1) short-circuits the input to the amplifier and (2) applies the output drift signal of the amplifier to a compensating storage capacitor. On subsequent actuation of the input and output switch devices, the compensating signal is superimposed on the data signal stored on the corresponding memory device.
A capacitive read only memory operable to respond to the logical product of the inputs to the memory. The read only memory consists of a pair of plates or memory planes capacitively coupled together. Circuitry logically inverts the input pulses to the first plane and selective capacitor placement creates pulsing on all outputs from the second plane except on the desired output. Circuitry logically inverts the pulses from the second plane resulting in an output which is the logical product of the input signals.
A high-speed acquisition system employing an analog memory matrix is provided in which sample-hold elements connected to an analog bus are arranged in rows and columns to form an M.times.N matrix. The system is operable in a fast in-slow out mode, and the analog memory matrix may be implemented on a single integrated-circuit semiconductor chip.
A system stores program instructions and other data in a single memory device, such as a flash ROM, by adjusting a processing speed of a microcontroller during write operations. Adjusting the processing speed renders the time involved in writing to the memory device shorter than the fetch time. This allows the microcontroller to write data to the memory device and execute instructions stored on the same memory device.
A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.
