Raw data relating to a variety of parameters is analyzed to determine whether or not the current value or condition of the parameter is significant according to schedules of criteria which are subject to change. Criteria selection is adaptive, being dependent upon modes or conditions indicated by the parameter values being handled by the apparatus. Additionally, certain criteria may have floating limits, so that the base from which deviation is measured for the purpose of determining significance is adjusted whenever a significant condition (deviation from a base by more than a permissible amount) occurs. Additionally, fixed limits are provided, particularly for parameters of the type that can result in a dangerous condition whenever the value of the parameter exceeds certain upper or lower limits. A given parameter may be tested for both floating limit and fixed limit conformance, and provision is made to take similar as well as different action in dependence upon exceeding the different types of limits. Provision is made to transmit the data, in this embodiment to record it for further analysis at a later date, in dependence upon exceeding a fixed limit a number of times more than a number setable to indicate probable successive number of transients. Exceeding a fixed limit results in printing an identification of the parameter which exceeded a fixed limit together with Greenwich Mean Time at the time of occurrence and an indication of whether an upper or lower limit was exceeded. Thereafter, that parameter will not cause printing until such time as the parameter value again falls within fixed limits. The disclosure embodiment utilizes standard data processing components in a relatively simple data flow arrangement, will control provided by a parameter identification decode in a read only memory (hereinafter referred to as ROM) or large decoding matrix. The ROM provides for each given parameter: a transient index indicative of the number of probable transients, thereby to be ignored; floating limit deviations (referred to symbolically herein as deltas) for a plurality of modes, the correct one being selected in dependence upon a given mode of operation; the addresses of both upper and lower fixed limits for the given parameter; the address in storage of the previous value used as a base for floating limits; the address of current values in storage which permits storing the present value of the parameter until it can be determined, at the end of a scan of all parameters, whether or not these parameters are to be recorded; and the addresses of the transducers or sensors -- that is the actual input equipment -- with which the parameter is related. Any parameter can have more than one parameter identifying number, so that polling of parameters can include more frequent polling of certain key parameters interspersed with sequential polling of all parameters, simply by providing the same connections for additional parameter numbers as may be provided for the basic parameter number for a given parameter. Progression of logical sequence and control is provided simply by a parameter counter which counts successively for each parameter analysis period, thereby polling the various parameter numbers in sequence, together with a program counter which identifies four different function periods, each subdivided into eight times, there being clock signals to identify first and second halves of each of the clock times. Provision is made to utilize main storage as a printer buffer storage as well as a one-scan recorder buffer storage.
A device for generating a histogram from a varying digital input word and for displaying the histogram as a series of vertical segments on a television monitor. The input word may be any word existing in a computer, e.g. it may be the program counter, thus to produce a histogram showing the frequency of occurrence of addresses of instructions used by the computer. The device includes a memory having a number of discrete memory addresses. One or more input words are assigned to each memory address, as preset by base address and resolution controls, and each time such word or words occur, the memory location at that address is incremented to produce a histogram. To display on a television monitor the histogram in memory, an X-axis position counter produces a series of counts during each horizontal scan of the monitor beam, to address successive memory locations during counting, so that each count corresponds to one memory location and also to a discrete X-axis position of the beam. A Y-axis position counter generates a count representing the Y-axis position of the beam. For each X-axis position, the content of the memory location associated therewith is read into a comparison circuit and compared with the Y-axis beam position. If the memory content of the addressed location is sufficiently great relative to the beam Y-axis position, the comparison circuit produces a pulse used to create a spot on the screen at the X and Y coordinates in question, so that as scanning progresses, the histogram segments are traced out on the screen.
The system includes: a number of subassemblies, each containing a set of switches connectable at their pair of inputs to different sources of analog signals and containing a multiplexer/decoder having outputs connected to different switches for their selective actuation; a differential amplifier having a pair of inputs connected to the pair of outputs of all of the switches; analog/digital converter means having its input connected to the output of the amplifier and having outputs providing multi-bit digital information; and control means that provides various functions.
Control system enabling the monitoring of a set of elements, more particularly a multi-recorder ensuring the monitoring of the junctors in a telecommunications exchange, comprising a live memory containing the data reflecting the situation of the elements, annex circuits enabling the distributing and processing of the said data and logic operators preferably formed with diode matrixes receiving simultaneously outside data coming from the monitored elements and internal data coming from the memory and ensuring the internal monitoring of the system and the monitoring of the said elements.
A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for application to each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.
A method for controlling equipment in a semiconductor fabrication system is provided. A host computer automatically receives actual data indicative of an actual state of a unit of equipment for fabricating semiconductor devices. The computer retrieves from a data base stored data indicative of a stored state of the unit. A state change is computed by comparing the actual data with the stored data and the state change is checked against a predetermined threshold. If the state change exceeds the threshold, the data base is updated by storing the actual data, and operation of the equipment is modified. If the state change does not exceed the threshold, the method returns to receiving actual data.
