There is disclosed a memory in which there are no fixed relationships between received addresses and storage locations. In some modes of operation, fixed relationships may be established and maintained, but subsequently changed. In other modes of operation, the receipt of the same address in successive memory cycles controls access to different sequential storage locations. In such modes of operation, some of the bits treated by the CPU as address bits are actually interpreted as representing instruction codes. When the memory is operated in one of the latter modes, long messages may be stored in buffer areas of the storage while "using up" only a greatly reduced area of the computer address space.

This hierarchical memory system has two memory units on each level. One of the units called the data store contains all the data at that level of the memory. The other unit called the copy back store contains all the changes that have been made in that data either by addition or modification. While the data store is interfaced with the next higher level in the hierarchical memory system or with the processing units for the data processing system, the second or copy back store can transfer the changes made in the data into the next lower level in the memory hierarchy system if the copy back store is free and the data store in the next lower level is not involved in transferring data up the hierarchy. The data store and the copy back data store in each level are on two different power systems and transfers of the changes to the next lower level are done in the order in which the change entered in the copy back store with the oldest entry being the first to be copied back.

Memory system comprising a first memory and a second memory, in which memories a plurality of memory elements are arranged according to word locations and can be addressed by an address signal per word location, further comprising for each memory an instruction line for read and/or write instruction signals, driving devices and terminals in each memory which are interconnected by a data path line, and a control device capable of generating the instruction signals for addressing word location in the first memory for transferring information associated therewith as an information word via the data path line between the two memories.

A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.

Updated images of messages are passed between asynchronous digital processors using dual port shared memory. In the basic form of the invention, three buffers in shared memory are assigned to each message. Where one of the processors is a controller for a data link channel carrying n messages, 2n+1 buffers are provided in free shared memory space with 2 buffers assigned to each message at all times and a common buffer serving as the third buffer for all of the messages. Where linked buffers in local memory of a controller processor receive message updates from a data highway, two buffers in shared memory are assigned to each message and a linked buffer in the controller local memory serves as the third buffer. The buffers containing the message updates are passed between processors by use of a buffer status array in shared memory. A semaphore lock in the array permits only one processor at a time to assign or release buffers.