In a system wherein a number of computers are coupled to a common bus and the communication among them is effected through the bus, a data transmitting apparatus with which, when a plurality of computers have simultaneously made requests for communication with another computer, the communication is made possible from one of the highest priority level, said data transmitting apparatus being constructed such that larger addresses in binary codes are assigned in the order of the priority levels of data to be transmitted. The address is successively transmitted from an upper-place bit in case of transmitting it to said bus; it is compared with an address on said bus at every bit; and in the case where said address of said apparatus is "0" without coinciding with said address on said bus, said apparatus prohibits transmission of signals ob bits of lower places than the non-coincident place.
A method of control of a data processing system whereby priority-controlled selection of one of a plurality of functional units with different connection priorities and which may be simultaneously signalling requests for connection to a common processor allocated thereto is effected by allocating to each functional unit a unique request signal for connecting that unit to the common processor with the request signal identifying the degree of priority of that unit and by providing means comparing and selecting the request signal having the highest priority where several request signals are being received by the common processor.
A read-out signal generator supplies read-out signals through a read-out bus bar to sources of first data signals and buffer memories storing second data signals produced by accompanying central processing units (CPU's) to make the read-out bus bar transmit also the first and second data signals in timed relation to the read-out signals. A coupling device supplies read-in signals with reference to the read-out signals and transfers the first and second data signals from the read-out bus bar to a read-in bus bar, which supplies the transferred data signals to the CPU's in predetermined time relation to the read-in signals. The coupling device may either be a mere connection (in which case the read-out signals serve as the read-in signals) or a data bank.
An asynchronous bus for self-determined priority of communication among master computer devices communicating with slave devices through said bus where a multi bit data channel and a multi bit address channel are shared between all of said devices. A logic circuit in each said master device is connected to each of three signal lines common to all logic circuits in all of said master devices. One of the three lines is connected in series in the order of assigned priority between master devices. Means are provided to actuate the logic circuits via the three signal lines to limit access to said bus in the order of assigned priority and to signal to other master units bus availability and to transmit an access granted signal to master units down stream of a user unit with only one logic gate delay per downstream unit.
Contention among a plurality of synchronous and asynchronous devices connected to a shared communication medium for access to time slots in a sequence of frames is resolved by assigning a unique priority word including a priority code prefix to each device and granting access to a given slot by comparing the values of the priority words assigned to competing devices. The priority code prefix is assigned as a joint function of whether synchronous or asynchronous communication is desired and whether synchronous communication is being initiated or continued. In each assignment protocol, synchronous communication is enabled by assuring any device that initially gains access to a particular time slot continued access to the same slot in succeeding frames. If desired, devices with synchronous access may relinquish unused time slots to asynchronous traffic, while reserving the ability to resume synchronous communication.
A novel method and apparatus for quickly allocating channels on a TDM (time division multiplex) bus to devices requesting access to those channels. In one embodiment, each channel of the TDM bus consists of nine bits and each device has a unique eight bit identification code plus one status bit (referred to collectively as a unique nine bit device code). If a channel is not occupied, each device wishing to gain access to the channel applies its own unique nine bit device code to the bus in the channel time period, sequentially, in order to significance. While doing this, each device monitors the bus to determine what code signal is on it; as soon as it detects a code bit differing from its own, it declares a conflict and stops sending its code, only to wait for the occurrence of the next channel when it retries. The device that is successful in applying all the bits of its code to the bus without conflict declares itself to be the winner, and on the next appearance of that channel (i.e. in the next frame) it transmits as the first bit in the channel a status bit set to alert other contenders for the channel that it is taken.