Multilevel digital signals are converted to binary signals and are transmitted as such. The binary signals are integrated by the frequency characteristic of a transmission line of narrow bandwidth. The transmission line converts the binary pulses to a multilevel signal. The receiver receives the transmitted multilevel signal and converts it to analog signals.
An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.
An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.
An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.
