A memory element which is an improved version of the known FAMOS (floating avalanche-injection metal-oxide-silicon) memory elements in that memory erasure is effected electrically. The structure of the known FAMOS memory elements is modified by having at least one diffused region in the silicon substrate which is isolated from the elements gate and drain electrodes, which is of opposite conductivity type to the substrate, and which is situated adjacent to the channel region between the gate and drain electrodes. At least one region of the substrate situated adjacent to the channel region is also isolated from the gate and drain electrodes, the buried gate of the FAMOS structure partially overlaps these isolated regions and a second gate is provided on the surface of the dielectric layer of the FAMOS structure such that it is above and completely overlaps the silicon gate.

A random access memory cell for storing information in both volatile and nonvolatile form is described incorporating a dual gate variable threshold transistor, a capacitor, and three field effect transistors. The dual gate variable threshold transistor may include a fixed threshold and a variable threshold field effect transistor.

A memory system utilizing an array of dual gate variable threshold MNOS memory transistors is disclosed which may be operated such that a single MNOS transistor is used to store each bit of digital information or in a second mode which utilizes two MNOS transistors for each bit stored. The threshold of the transistor interrogated is used to determine the state of a flip-flop comprising a pair of cross-coupled MNOS transistors. A particular transistor of the array is interrogated by coupling appropriate "row select" and "column select" signals to the row and column select terminals. Transistors comprising the first and second columns have their source terminals connected in common and to the drain terminal of the first transistor of the cross-coupled pair. Similarly for, the third and fourth columns. First and second reference transistors also have their source terminals respectively coupled to the drain terminals of the first and second transistors comprising said cross-coupled pair. In either mode, the cross-coupled pair is utilized as the sensing circuit for determining the threshold state of the MNOS memory transistor interrogated. The circuitry coupled to the drains of each transistor comprising the cross-coupled pair is identical resulting in a symmetrical circuit.

A memory cell combining CCD and MNOS technology comprised of a MNOS transistor having a reversible, electrically shiftable threshold wherein its memory-controlled gated source is connected in series with a MOSFET address switch transistor, with the address switch transistor and MNOS memory transistor being coupled in parallel with a CCD shift register stage by means of respective P+ diffused regions within separate wells of the CCD shift register. Preferably, each CCD shift register stage includes two receiving potential wells capable of holding minority carriers defined by two regions acting as barriers to the flow of minority carriers and having a multi-phase drive system operating the shift register. The non-volatile memory thus configured provides non-volatile storage outside the CCD shift register, in which the CCD signal charge controls the (memory write) address switch; and memory read-out is accomplished by parallel data charge injection via the memory-controlled gated source, with no logic inversion.

A semiconductor memory element comprising a semiconductor substrate and an insulating layer thereon, a charge storage element located on a portion of the insulating layer and separated from the semiconductor substrate, and first device means for injecting hot electrons from the semiconductor substrate into the insulating layer portion to write a first charge state on the charge storage element and second device means for injecting hot holes from the semiconductor substrate into the insulating layer portion to write a second charge state on the charge storage element.