A subsystem of binary circuits, packaged in modular form and having a plurality of connection points through which it is incorporated into a master system such as a digital computer, is tested by utilizing a binary word generator that periodically generates a string of parallel binary bits for application to the subsystem under test. Output signals from the subsystem under test are continually monitored and supplied to the binary word generator to shape the character of the succeeding string of parallel binary bits (binary word) applied to the subsystem. If there are no faults in the subsystem under test, starting the word generator and the digital circuits in the subsystem from respective initial reference states, insures that the binary word applied to the subsystem by the word generator, after a certain number of word applications or periods, will always be the same, for the same initial states and number of periods. A different binary word, than the one expected for a subsystem having no faults, is generated at the end of a test cycle when an identically structured subsystem having a fault or faults therein is tested under the same initial conditions and number of periods. To isolate the fault-containing portion of a subsystem when the expected word is not generated, the output connection points of the subsystem are disconnected from the input connection points of the binary word generator, the binary circuit subsystem and word generator are placed into an initial or reference state, and the binary signals appearing at each output connection point of the subsystem are counted during a cycle of word applications by the word generator. The count of binary signals generated at each output connection point of the binary subsystem will always be the same number for the same number of word applications and the same set of initial states for the binary word generator and the subsystem, if there are no faults in the subsystem. If there is a fault in a circuit connected to a particular output connection point of the subsystem, the count of binary signals appearing at this point for one test cycle, (a particular number of word applications) will be different than expected, while the count at all the other output connection points will be the same as expected, assuming that the initial states of the binary word generator and the binary subsystem, and the number of word applications remained the same.
A built-in test system employs dual-mode feedback shift registers to supply test vectors and evaluate test responses of functional and interface networks of a logic system. Test responses are supplied to a quotient bit compressor which generates a system response signature for comparison with an expected fault-free signature to produce a system pass/fail status signal.
A functional testing system for programmable logic devices. Test vectors are generated by a shift register and applied to the contact pins of the logic device through isolation elements so that all pins may be treated alike regardless of whether they are inputs or outputs. The logic level on pins that are outputs are controlled by the logic device, while logic levels on pins that are inputs are controlled by the shift register. The response of the logic device to the test vector is recorded in an output shift register and the response is then shifted out of the shift register to one input of an exclusive OR gate that also receives outputs from predetermined stages of the test vector shift register to create a pseudo-random function. The output of the exclusive OR gate is shifted into the test vector shift register as each bit of the logic device's response is applied to the exclusive OR gate thereby creating a new test vector. The number of test vectors applied to the logic device is counted and when a predetermined number is reached, the test terminates and the current test vector is then stored and compared to the final test vector obtained by performing the same test on an identical circuit known to be operating correctly. The testing system thus evaluates the functionality of the logic device while also providing the stimulus to the device.
A path oriented decision making test pattern generator is embodied in a logic chip test system for testing large-scale integrated circuits having many internal nodes inaccessible to the test probes of chip testing machines. For each designated possible chip fault, consisting of a stuck-high or stuck-low voltage at a node of the chip logic network, the generator provides a test pattern of signals to be applied to the input pins of each chip, so that the resulting signal at an output pin indicates whether the fault is present in the chip.
In a system which measures a parameter of a sample and displays information relating thereto, a circuit including the component elements of the system for testing signal levels at test points within the system and for displaying the test signal levels. Switching means places the system in either a transducing mode for measuring the parameter or in a combined transducing/self-testing mode for simultaneous testing during transducing operation. The testing circuit includes an operator manipulated probe for contacting any of the test points and an analog multiplexer input of the system for multiplexing the probe test signal and the transducing signal. The multiplexed signals are converted to digital form and processed by the system's computer for display. In the combined transducing/self-testing mode, the probe test signal information is outputted to the system display while the transducing output thereto is inhibited. The transducing output information derived during testing is processed and stored by the computer for subsequent display.
A device for processing digital signals includes combinatorial and sequential logic elements. For the testing of the device, a shift register can be formed from the sequential elements. A test pattern is applied thereto. The result of the processing of the test pattern is applied to the shift register. The output of the shift register is connected to a second shift register which forms a moving multibit sum pattern from a received series of result patterns by way of a feedback circuit to at least one Exclusive-OR-element. An output of the feedback circuit is connected to an input of the first shift register in order to apply a subsequent test pattern thereto. After completion of the test, the sum pattern formed is checked.
