A circuit for comparing a known electronic circuit card with an unknown card of similar type wherein clock pulses are delivered to a multistage binary counter which delivers its output identically to the inputs of the known card and to the corresponding inputs of the unknown card. The corresponding inputs and outputs of the known card and unknown card are compared with each other by a plurality of exclusive OR-gates which generate an error signal in the event of any disagreement between the two cards. A disagreement signal causes the termination of the operation of the binary counter. This permits an operator to note the input or output of the unknown card that did not agree with the corresponding input or output of the known card and to repair the unknown card.
A testing apparatus employing a binary counter to supply identical signals to a tested and a standard reference circuit is disclosed. The tested includes a program controller, a self-contained power supply, analog and digital comparison circuits, along with output indicators for displaying the difference, if any, between the tested and standard reference circuit.
Improved means and methods are described for continuously and asynchronously testing the operation of a digital circuit or unit. The testing approach is based on determining whether an output signal from the unit under test is out of skew with a corresponding output from a standard unit for at least an adjustable predetermined minimum time period.
Portable tester and method for testing a variety of circuit boards without utilizing adaptor boards for re-routing input test signals and supply voltage from the tester to pins of the board under test. A plurality of edge adaptors having different pin spacings have their respective pins connected in parallel to corresponding edge connector stake pins. Each edge connector stake pin is connected to or isolated from the corresponding driver/sensor stake pin by means of a switch. Each driver/sensor stake pin is connected to the input/output terminal of a programmable driver/sensor circuit. A plurality of power supply stake pins are connected to various power supplies of the portable tester. Connectors coupled to the family board can be utilized to route power supply voltages to electrically isolated edge connector stake pins. Isolated driver/sensor outputs can be routed to other edge connector stake pins. A main processor stores a test program and transmits data and control information to predetermined driver/sensor circuits. A high speed processor is coupled between the main processor and the inputs of the driver/sensor circuits. The high speed processor memory can store a bus-defining subroutine containing a sequence of data shifting instructions which shift a word in the shift register to the input of specified driver/sensor circuits at high speed. The high speed processor can synchronize the operation of the portable tester with an asynchronously operating printed circuit board under test.
A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate. The test assembly re-drives the system clocks with a phase lock loop (PLL) buffer to a memory module socket on the test assembly to permit timing adjustments to minimize the degradation to the system's memory bus timings due to the additional wire length and loading. The test assembly is programmable to adjust to varying bus timings such as: CAS (column address strobe) Latencies and Burst Length variations. It is designed with Field Programmable Gate Arrays (FPGAs) to allow for changes internally without modifying the test assembly.
An integrated circuit (IC) testing system is provided by the present invention. The IC testing system is for testing a device under test (DUT) IC. The IC testing system includes an interface to a target system. The target system incorporates a known good IC (KGIC) which is identical to the DUT. The KGIC is implemented on the target system as it is designed to be used during the normal operation of the target system. The target system will then exercise the KGIC by running the diagnostic programs or by sending appropriate instructions or commands to invoke the KGIC to perform different functions for the target system. The interface system provided by the present invention for performing an IC test will then capture the signals to and from the KGIC on-the-fly. The testing system of the present invention will redirect the KGIC input signals to the DUT as testing input signals, i.e., input stimuli. The output signals generated by the will be used as the reference signals for comparison with the corresponding response signals from the DUT for fault detection.
