An electrically programmable semiconductor read only memory array which utilizes a floating gate metal-oxide-semiconductor (MOS) device as a storage element is described. The floating gate of the device (storage element) may be negatively charged by avalanche injection. A field effect transistor is coupled in series with the storage element to form a single memory cell. A plurality of cells comprise an array. The gate of the field effect transistor is coupled to an X-line of the memory array and one of the other terminals of this transistor, in one embodiment, is coupled to a Y-line of the array. The array is electrically programmed by application of information to the X and Y lines of the array.
A non-volatile memory circuit which may be formed on the same memory chip as a MOS integrated circuit for an electronic watch. The non-volatile memory circuit includes a power source and a high voltage application terminal for writing data. A non-volatile memory device is coupled between the power source and the high voltage application terminal. A voltage limiting circuit for limiting the voltage applied to the non-volatile memory is coupled between the power source and the high voltage application terminal. A current limiting circuit for limiting the current applied to the non-volatile memory is coupled between the high voltage application terminal and the non-volatile memory, whereby the non-volatile memory is protected from stray voltage and current writing data into the non-volatile memory. The invention may also be applied to an EEPROM arrangement in which the data may be read to or erased from the non-volatile memory without erroneous writing or erasure due to static noise or other outside noise.
An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.
A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. Very small cell size is provided by a triple level polysilicon structure.
A nonvolatile semiconductor memory device is obtained of which tunnel oxide film can be made thinner and which can allow low voltage and power consumption. P type polycrystal silicon is used as a floating gate electrode. Thickness of a tunnel oxide film (first insulating film) is set to less than 10 nm. By using P type polysilicon as a material of the floating gate electrode, a barrier height of a well-type potential is increased from 3.1 eV to 4.4 eV, and thus the leak current is effectively prevented. Thus, the film thickness of the tunnel oxide film can be made less than 10 nm, and operating voltage can also be lowered. Therefore, reduction in power consumption and improvement in performance of the nonvolatile semiconductor memory device can be achieved.
An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.
