This invention is an improvement to an integrated circuit package which is of a type that includes a package body with multiple chip attach regions for holding respective integrated circuit chips, signal pads around the chip attach regions, an array of I/O pins on the package body, a first set of conductors in the package body which selectively connect some of the signal pads to the I/O pins, and a second set of conductors which selectively connect some of the signal pads to each other but not to any I/O pins. This improvement enhances the testability of the package at its intermediate state of manufacture, and it comprises: (a) a test region in the package body which is spaced apart from the I/O pins, the chip attach regions, the signal pads, and the first and second sets of conductors; (b) an array of test pins which is attached to the test region of the package body; and (c) a third set of conductors which are disposed in the package body that selectively connect the I/O pins to the signal pads and the first and second sets of conductors such that all conductive paths can be tested for shorts and/or opens via the test pins and the I/O pins. Then, after testing is complete, the test region of the package body is permanently removed from the remainder of the package by a step such as sawing.

LSI (large scale integration) semiconductor chips have two sets of Schottky diodes formed therein for assuring electrical contact between the chip voltage supply and I/O (input-output) signal contacts (or pads) and test probes. The diodes of one set form an AND circuit having the diode inputs coupled to respective chip input signal contacts. The other set of diodes have first terminals coupled to the output of the AND circuit, and have second terminals, each coupled to a respective chip output signal contact. When a plurality of test probes are brought into contact with the chip I/O and voltage supply contacts preliminary to running static and/or dynamic tests on the chip circuits, a selected signal level is applied concurrently to all probes which are connected to chip input signal contacts and to probes connected to the supply contacts. If there is good electrical contact between these probes and each of the input and supply contacts, a selected signal level (e.g. UP) appears at the output of the AND circuit. This output signal is then applied by the AND circuit (or an amplifier) to each of the chip output contacts via a respective diode in said other set, irrespective of the states of the functional logic on the chip. If good electrical contact exists between the chip output contacts and their respective probes, the UP output signal level will appear on all of the latter probes. Detection of the UP signal level on all of the latter probes indicates good contact between all probes and chip contacts. Once this is established, functional testing of the chip circuits can begin.

A structure for selectively externally accessing mechanically difficult to access circuit nodes in an integrated circuit by the combination of an externally accessible circuit terminal and a plurality of connecting means, each of which connect a particular circuit node which is difficult to access to said terminal. Each of the connecting means includes a photoconductive semiconductor device which is normally electrically nonconductive but which is adapted to electrically conduct when subjected to localized light such as a laser beam. When the particular photoconductive device is rendered conductive, it in turn makes the connecting means associated with it conductive and, thereby, provides a conductive path from the particular circuit node to the externally accessible terminal.

This specification describes the testing of interconnections between modules mounted on a card and between the modules and the input and output terminals of the card. Each of the modules has an Exclusive-OR circuit which receives an input from each of the input pins of the module and has a single output which is taken off an output pin of the module. Also, each of the modules has a test input circuit for accessing all of the output pins of the module in parallel from a single input terminal. The test input circuits are used to apply a binary 0 followed by a binary 1 to all the outputs of all the modules. The Exclusive-OR circuits are used to monitor the response to those signals. By testing in this manner, all the connections between the modules and also between the modules and the card terminals can be checked for stuck ones and zeros. In the preferred embodiment a more complex but still relatively simple bit pattern can test all the interconnection nets to determine if there are shorts between any of the nets.

A method and apparatus for contact testing a plurality of devices under test, either sequentially or simultaneously. In a first test phase it is determined whether the test probe to each contact is shorted to the most negative rail. In a second phase it is determined whether the test probe has made proper contact, and whether ESD diodes on the devices under test are functional. In both test phases a negative pulse is generated on a tester bus and applied to the contact by the test probe. In the first test phase the positive rail of the device under test is grounded; in the second test phase the positive rail of the device under test is made positive. The negative rail of the device under test is connected to the negative rail of the tester. In both test phases, upon termination of the negative pulse, the bus is restored to a positive voltage which is dependent upon the condition of the contact and the condition of expected input devises at the contact. The bus voltage as measured in accordance with a logic which determines the condition of the contact and the condition of expected input devices at the contact. Data signals for functional testing of the device under test are can be applied to the bus through an isolating driver which preserves he bolt of the contact test.