A floating gate solid state storage device comprising a floating silicon or metal gate in a field effect device which is particularly useful in integrated circuit devices such as a read-only memory is disclosed. The gate which is surrounded by an insulative material such as SiO.sub.2 is charged by transferring charged particles (i.e., electrons) at relatively low voltages (e.g., less than approximately 50 volts) across a thick insulation layer (e.g., greater than approximately 500 angstroms) from the substrate during an avalanche injection condition.
Semiconductor memory device in which charge carriers are injected between a semiconductor surface and a gate electrode separated from the semiconductor surface by an insulating layer to effect a change in the characteristics of the device. According to the invention for the storage of information a depletion zone is formed across which a voltage drop is applied which is lower than the voltage at which avalanche multiplication occurs, but higher than the potential barrier for the charge carriers at the interface between the insulating layer and the semiconductor material, while charge carriers are injected into this depletion zone by means of a p-n junction or by radiation.
An MOS memory cell which includes a floating gate charged from the substrate by avalanche injection. Charge is removed from the floating gate to an erasing gate by tunneling. Sharp edges on the polycrystalline silicon floating gate provide an enhanced electric field to overcome the silicon/silicon oxide barrier, thus permitting charge to be transferred from the floating gate to the erasing gate.
A field effect semiconductor memory apparatus with a floating gate which is so constructed that when a gate electrode is impressed with voltage, there is created across the floating gate and substrate an electric field stronger than, or at least as strong as, that prevailing across the floating gate and gate electrode, whereby the floating gate is stored with information by being impressed with a relatively low level of voltage and the stored information is extinguished by giving rise to an avalanche breakdown across the substrate and at least either of the source and drain.
Avalanche injection type MOS memory having a floating gate surrounded by an insulating layer between the source and drain regions formed on one side of a semiconductor substrate wherein there is formed one or two auxiliary semiconductor regions with the same type of conductivity as, but with higher concentrations of impurities than, said semiconductor substrate in the channel region thereof defined between said source and drain regions so as to contact either of these regions.
A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.
