The present invention includes a first input signal circuit to receive pulse signals from a voltage-controlled oscillator (VCO), or some other controllable pulse signal source, and a second input signal circuit to receive pulse signals from a magnetic recording medium, or some pulse signal source, with which the voltage controlled oscillator is to be put in phase synchronization. A correction signal generator circuit is connected to both the input signal circuits to provide a first correction signal in response to a pulse signal from the recording medium and to provide a second correction signal in response to a pulse signal from the VCO. There is a third circuit which monitors how long a correction signal is in effect and if such a correction signal is present for longer than a predetermined time, the third circuit terminates the correction signal to enable a new correction signal to be generated in response to the next one of said input signals to arrive. Finally, there is a fourth circuit which is connected to the correction circuitry to permit it, in a first mode of operation, to be enabled at all times to phase correct the controllable pulse signal source in response to a predetermined pattern of signals from the recording medium and to permit it, in a second mode of operation, to be available only during "window" periods initiated by pulse signals from the recording medium.

An all-channel PLL tuning system includes LOF counters, a comparator producing an equality pulse each time the LOF count matches a preselected channel number count and a digital phase-frequency comparator comparing the equality pulses with reference pulses. High speed tuning is accomplished with the phase-frequency comparator arranged to yield immediate correct directional information. A reset pulse is generated for every other equality pulse and forces the equality and reference pulses to have the same initial phase and the digital phase-frequency comparator into one of its stable states corresponding to the desired output condition. The output directional information from the phase comparator is stored and tuning proceeds at high speed until a change in directional information occurs, indicating that the correct tuning frequency has been passed. Normal PLL operation then ensues.

The comparator comprises a circuit for detecting the sign of the phase-shift of the reference signal relatively to the second signal for a predetermined phase of the latter. It delivers a corresponding binary phase difference signal. A second circuit selects those changes in values of the phase difference signal which occur for a phase of the reference signal comprised in a predetermined phase interval, and are thus surely representative of a change in the sign of the frequency difference.

A phase detector which employs four memory elements suitably comprised by D-type flip-flops. The detector provides an output dependent upon the phase difference between two input signals. One pair of memory elements is clocked by one input signal. The other pair of memory elements is clocked by the other input signal. The memory elements are so arranged that when the ratio of the frequencies of the input signals is less than 2:1, the detector provides three output states which may be used in a phase locked oscillator to cause, in the first state, an increase in the frequency of one input signal; in the second state, no frequency change; and in the third state, a decrease in frequency. Above a frequency ratio of 2:1, the detector never enters the second state. Elimination of the second state under such conditions decreases the time required for a phase locked oscillator with this detector to achieve phase lock.

A digital frequency comparator circuit comprising two counters connected to a circuit to be driven, in which one of the two counters which earlier issues an output signal is temporarily held, and both the counters are not cleared until the other counter subsequently issues an output signal, whereby an instability in the operation of the circuit to be driven is eliminated.