or
Bookmark and Share
   
Document Number
US Patent 3764997
Issued Date
October 9, 1973
Link
Inventors
Map
Abstract
In an input device for use in an electronic computer or the like, it is preferred to transfer the informations fed from a plurality of the information sources to the following stages at the predetermined periods, and in the event that two or more informations are applied to the input device simultaneously in an overlapped condition, it is necessary to transfer each of the informations independently to the following stages to prevent erroneous operations. In accordance with the input device of the present invention, an information signal fed from a selected one of a plurality of the information signal sources is stored in a shift register, on the other hand, the subsequent information signal is prohibited from entering to the shift register while the former information signal is stored in the shift register, and the information signal thus stored in the shift register can be read out at a predetermined period convenient to the following stages.
Drawing
INPUT DEVICE - US Patent 3764997 Drawing
Drawing from US Patent 3764997
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
5
Comments:
no comments yet
Owner
Omron Tateisi Electronics Co. (Kyoto-shi, Kyoto-fu,JA)
Published
October 9, 1973
Application Number
05/219,350
Filed
January 20, 1972
US Classification
341/34  
Int'l Classification
G06F   3/023   (20060101)   H03M   11/00   (20060101)   H03M   11/20   (20060101)  
Examiner
Assistant Examiner
Priority Data
Jan 23, 1971 [JA] 46/2077
USPTO Field of Search
340/172.5  
Related Patents
4266278 - Portable electronic device equipped with calculation and timekeeping functions - Owned by Citizen Watch Co., Ltd. (Tokyo,JP)

A portable electronic device with calculation and timekeeping functions, equipped with a keyboard for calculation and time setting purposes, means for producing scanning signals when a key is actuated, these signals being applied to switching elements connected to rows of keyboard contacts. When a key is depressed, the resultant high level signal potential applied to the corresponding contact row causes the row position to be detected and stored in a first memory circuit, which produces a signal causing the corresponding contact column to be detected and stored in a second memory circuit. Actuation of an external control member causes a signal to be stored by a reset signal in a first stage memory circuit which produces an output signal to be subsequently stored in a second stage memory circuit in synchronism with a timing signal. The low frequency and low duty cycle of the scanning signals and reset signal ensure minimized power consumption and suppression of switch bounce effects.

4199750 - Key input circuit capable of roll-over operation - Owned by Hitachi, Ltd. (JP)

In a key input circuit, the key input signal is serialized and applied directly and through a circulating register working with a certain delay time to one gate for transmitting the direct key input signal and to another gate for transmitting the output of the register utilizing the other signal as an inhibitation signal. The output of the one gate is supplied to an output means which allows the passage at a predetermined time later and the output of the another gate is used to erase the corresponding contents of the register at a predetermined time later. This erasing is inhibited for a predetermined time period to allow a new key input signal.

4164666 - Electronic apparatus using complementary MOS transistor dynamic clocked logic circuits - Owned by Toyko Shibaura Electric Co., Ltd. (JP)

An electronic apparatus comprises a timer circuit driven for a given time in response to a key input, complementary MOS transistor clocked dynamic logic circuits each with an output storage capacitance, clock signal supply souce for supplying complementary clock signals to the clocked dynamic logic circuits during the operative period of the timer circuit, and for supplying voltages with fixed levels to the clocked logic circuits during the inoperative period of the timer circuit. During the inoperative period, the output capacitance of the clocked logic circuit is fixed at a fixed potential level. This prevents the simultaneous turning-on of the complementary transistors in a succeeding logic circuit connected to the clocked logic circuits, resulting in little power consumption even when a power switch is not used.

Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us