A detector to detect two identical addresses during the same cycle in a TDM switching system has a one-bit location added to each different address word storing row of a control memory. Each address word sent by a cyclically operating addressing memory to a speech signal memory is also sent to the control memory and a logic 1 is written into the corresponding one-bit location. The logic 1 appears only at write time. At all other times a logic 0 appears in the one-bit location. This writing operation is preceded by a reading operation of the addressed row. Each row is read one time per cycle so that logic 1 is only read if there are two or more writing operations in the same row during a cycle.

A method and circuitry for masking data in a memory device are provided, which detect whether at least one failed bit location within the memory device is equal to a corresponding bit within input data. Data is written to the memory device as selectively inverted from the input data based upon whether the failed bit location is equal to the corresponding bit. An inversion bit within the memory device is selectively set to indicate whether the written data is inverted from the input data.

A parity checking scheme for detecting memory array word line failures whereby all of the data and parity bits of a plurality of bytes sharing the same word line erroneously assume the value "1" or the value "0". When storing data in the array, the data and parity bits comprising each byte are stored directly except for the parity bit of a selected one of the bytes, which parity bit is inverted by a gated inverter circuit before storing. The same gated inverter circuit also inverts the parity bit of the selected byte upon reading the stored data. All of the remaining bits of all of the remaining bytes are read directly. The read bits of each byte are applied to a respective parity checking circuit of the same even or odd parity type as is used in storing the data. The outputs of all of the parity checking circuits are applied to error control logic.

Registers are inclined to react to any interference as follows: if any one stage inverts, the entire register inverts. In one embodiment, one additional bit is associated with the register, which bit is used to indicate that interference has occurred. Registers may then be inverted to their original form or may, by equating the meaning of the inverted form of the information contents of registers to the original form, ignore disturbance(s) caused by interference. Information media such as magnetic or optical discs for storage of such information thereon are also disclosed. The invention brings order to information failures caused by interference and thus is able to use such failures as opposed to other approaches which fight such failures. The invention avoids the need to keep track of original and inverted forms of information, independent of interference.

The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value "1." This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.