The phase sequence of the phase currents supplied by a three-phase AC power supply to a phase-sensitive load (such as a three-phase AC motor) is monitored by developing three phase-displaced, rectangular shaped logic signals, respectively representing the three phase currents, and applying these logic signals to respective ones of the J, C and K inputs of a J-K flip-flop. When the load is correctly connected to the power supply, the phase relationship of the three logic signals will be appropriate to trigger the flip-flop to its set operating state. Any other sequence actuates the flip-flop to its reset state which, in turn, disconnects the load from the power supply.

A circuit for producing a periodic sawtooth signal comprising an oscillator which is directly synchronizable by synchronizing pulses and the natural frequency of which is approximately equal to the repetition frequency of the pulses in the synchronizing absence of synchronizing pulses. At a phase difference between the sawtooth signal and the synchronizing pulses which exceeds a predetermined value the supply of synchronizing pulses is inhibited and a frequency correction circuit is made operative, causing the natural frequency of the oscillator to change. When the said phase difference becomes smaller than the predetermined value the frequency correction is switched-off and the synchronizing pulses are applied to the circuit so that direct synchronization is effected.

The present invention is directed to a digital PLL (phase locked loop) circuit. A phase of an output clock is advanced by about 360.degree. at every master clock. Only when there is a data edge having a large input level, a phase difference is calculated and the output clock frequency becomes a frequency deviated amount. Therefore, an electric power consumption can be reduced and an AGC (automatic gain control) function is presented in the input data. Further, the digital PLL circuit can be given free running control and leakage secondary PLL characteristics so that the digital PLL circuit can be enhanced in efficiency. Therefore, there is provided the clock reproducing digital PLL circuit of high efficiency which can reduce an electric power consumption.

The coincidence circuit includes negative and positive signal processing means. The negative and positive signal processing means each includes level detector circuit means for developing separate level detector output signals for each one of a plurality of a-c input signals when each one of the plurality of a-c input signals is of a negative or positive value respectively greater than predetermined negative or positive threshold levels. The predetermined threshold levels are of different magnitude for at least some of the a-c input signals. AND circuit means is coupled to receive the level detector output signals of the negative and positive signal processing means for developing AND circuit output signals respectively representative of negative and positive phase coincidence of the a-c input signals with threshold level attainment. OR circuit means is coupled to receive the AND circuit output signals for developing an OR output signal continuously representative of the phase coincidence of the a-c input signals. The coincidence circuit operates directly from a-c input signals of relatively low signal strength. In a preferred embodiment, a plurality of comparators are employed to receive four a-c input signals for use in a ground distance protective relaying application. In this embodiment, the predetermined threshold levels are in the millivolt range. Other embodiments are disclosed.

A phase sychronizing circuit for a device which reproduces digital data has a phase locked loop including a first phase comparison circuit, a voltage controlled oscillator (VCO) producing an output the frequency of which is controlled by the first phase comparison circuit, and a first frequency divider to divide the output frequency of the VCO. The phase synchronizing circuit further includes second frequency divider for dividing the output frequency of the VCO, a second phase comparison circuit for comparing the phase of a first clock signal from the first frequency divider, with that of a second clock signal from the second frequency divider and a circuit for controlling the frequency dividing ratio of the first frequency dividing circuit according to the phase difference between the first and second clock signals in such a way that the frequency dividing ratio becomes one of 1/N, 1/(N+1) and 1/{(N+(N+1))/2} wherein N is a positive integer.