A large scale integrated circuit with external integral access test circuitry having a semiconductor body with a surface. A large scale integrated circuit is formed in the semiconductor body through the surface and comprises a large number of interconnected circuit elements with a large number of input and output pads connected to the circuit elements and disposed near the outer perimeter of the semiconductor body. An integrated test circuit is formed in the semiconductor body and extends through the surface. The integrated test circuit has a plurality of probe pads carried by the semiconductor body and connected to the test circuit. The integrated test circuit is formed external of but in relatively close proximity to the large scale integrated circuit. Leads are provided on the semiconductor body which connect the integrated test circuit to the large scale integrated circuit whereby access can be obtained to the large scale integrated circuit through probing of the probe pads of the integrated test circuit to ascertain the characteristics of the large scale integrated circuit.

A contact check circuit of a semiconductor device includes N-channel MOS transistors connected in series between pads located at opposing ends, with their gates respectively connected to intermediate pads. At the contact check, conduction between opposing pads is checked, applying an "H" level to probes corresponding to the pads. Thus contact between the pads and probes of a semiconductor testing apparatus can be checked at once.

A method for inspecting a printed circuit board having through-holes filled with conductive paste and having a pair of current measurement lands and a pair of resistance measurement lands. The pairs of current measurement lands and resistance measurement lands are used to measure voltage and current through the through-holes using the four-probe method, thereby preventing incomplete inspection of printed circuit boards and improving the dependability of tests on the packing conditions of the conductive paste in the through-holes.

The purpose of the test method is to improve test efficiency in a semiconductor test method utilizing multiprobing. The semiconductor test method involves placing probes into contact with the electrode pads of semiconductor chips on a semiconductor wafer with a test head providing and receiving test signals through the probes thereby checking the electrical properties of the semiconductor chips sequentially. According to the test method, in order to test a plurality of adjacent semiconductor chips simultaneously, as many probes are provided as the number of semiconductor chips to be tested simultaneously, the test head is capable of providing and receiving test signals for the plurality of semiconductor chips simultaneously, and the number of semiconductor chips that are tested simultaneously is determined without being limited to a power of 2.

This specification describes the testing of interconnections between modules mounted on a card and between the modules and the input and output terminals of the card. Each of the modules has an Exclusive-OR circuit which receives an input from each of the input pins of the module and has a single output which is taken off an output pin of the module. Also, each of the modules has a test input circuit for accessing all of the output pins of the module in parallel from a single input terminal. The test input circuits are used to apply a binary 0 followed by a binary 1 to all the outputs of all the modules. The Exclusive-OR circuits are used to monitor the response to those signals. By testing in this manner, all the connections between the modules and also between the modules and the card terminals can be checked for stuck ones and zeros. In the preferred embodiment a more complex but still relatively simple bit pattern can test all the interconnection nets to determine if there are shorts between any of the nets.