A generic sequential digital pattern generator is disclosed for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns. The generic invention comprises a decoding means connected to a serial data stream, for receiving a compacted pattern message and converting the message to a signal on one out of r decode lines, an output register having r binary storage cells connected to r output lines, and r modulo 2 adders in parallel. Each modulo 2 adder has an augend input and an addend input. Each augend input is connected to one decode line from the decoding means. Each addend input is connected to one input line from the register. When the decoding means receives a compacted pattern message, it executes a change in the binary state of a selected one of the r output lines. Two species of the invention are disclosed, a first digital pattern generator operating on a serial data stream of pattern messages compacted by a log.sub.2 r encoding scheme, and a second digital pattern generator operating on a serial data stream of pattern messages compacted by the Shannon-Fano encoding scheme.
An electronic system for testing an electronic device responsive to a data clock signal and to a serial input data signal synchronous with the data clock signal comprises an oscillator for generating oscillator pulses, a data clock signal generator responsive to oscillator pulses for generating the data clock signal, timing circuitry for counting oscillator pulses and for generating at least one input select signal indicative of the number of oscillator pulses counted, and multiplexing circuitry for receiving at least two parallel input data signals and for sequentially selecting the parallel input data signals in response to the input select signal or signals to generate the serial input data signal.
There are provided methods each of which is for efficiently compressing a test pattern to be applied to an IC for testing. The number of data changes .phi. and a data entropy H of a pattern for each pin of an IC are obtained and then the test pattern is divided and the divided patterns are distributed to a block for .phi. that is equal to or less than a threshold value .phi..sub.M (.phi.<.phi..sub.M), a block for .phi.>.phi..sub.M and for H that is equal to or less than a threshold value H.sub.M (H<H.sub.M), and a block for H>H.sub.M (411). The block for .phi.<.phi..sub.M is compressed by a run length compressing method, the block for .phi.>.phi..sub.M and H<H.sub.M is compressed by the run length compressing method after application of Burrows wheeler transform, and the block for H>H.sub.M is compressed by an LZ compressing method.
A parallel-processing apparatus includes a plurality of cells, variable-delay circuits, a signal output unit, a delay counter, and an accumulation unit. Each cell has a processing circuit for performing arbitrary processing. The variable-delay circuits change the signal propagation delay in accordance with the processing results of the processing circuits. The signal output unit outputs a measurement input signal to the first variable-delay circuit of a variable-delay circuit array. The delay counter receives the measurement input signal output form the signal output unit and a measurement output signal output from the variable-delay circuit array, and obtains the signal propagation delay time of the variable-delay circuit array upon the basis of the measurement input and output signals. The accumulation unit accumulates the processing results of the processing circuits. A parallel processing method is also disclosed.
A hierarchical complex logic tester architecture is disclosed which minimizes the encoding of program information for testing. The architecture takes advantage of the fact that much of the information applied as test signals to pins of a device under test, changes little from test cycle to test cycle. In one aspect of the invention, run length encoding techniques are used for identifying the number of test cycles over which a given test pin is to be maintained in a particular signal state. In another aspect of the invention, use is made of a small memory associated with each signal pin of the device to be tested. There may be a small plurality of for example, 16 different kinds of signals which can be applied to or received from a given signal pin of a device under test. The dedicated small memory associated with each device pin to be tested, will have the ability to store from one to 16 states. The current states stored in a dedicated-per-pin memory will enable one of the 16 different types of test signals per test cycle to be applied to the particular device pin. Thus, the types of signal driving or sensing for each of the plurality of pins for a device under test, need only be indicated once to the per-pin-memory over a large plurality of test cycles. This enables consecutive test cycles to be applied to the device under test under the control of a relatively small number of tester program words.
A cell switch and a cell switch network with a simplified cell switch testing such that the testing processes can be carried out quickly and easily. The cell switch includes a dummy cell generation circuit for generating dummy cells in correspondence to the output transmission paths; and an output control circuit for selectively outputting the dummy cells to the output transmission paths when a test of the cell switch is indicated by an externally provided control signal. In a cell switch network in which the cell switches are interconnected in a form of a multi-step configuration, the cell switches belonging to each step in the multi-step configuration of the cell switch network is tested sequentially, by supplying the control signal to each of the cell switches belonging to each step in the multi-step configuration of the cell switch network sequentially, in a reverse order of steps in the multi-step configuration of the cell switch network.
