A phase lock loop employs a frequency discriminator having a relatively slow response to pull a voltage controlled oscillator into frequency lock with an input signal. After frequency lock the output of the frequency discriminator is nulled and a phase detector becomes effective to maintain phase lock. The frequency discriminator utilizes an operational amplifier to which both the input and oscillator signals are capacitively coupled through respective oppositely poled diode gates. A feedback capacitor, which is much larger than the input coupling capacitors, has charge transferred thereto from each coupling capacitor during alternate half cycles of the input and oscillator signals. The net charge across the feedback capacitor is a measure of the frequency difference between the input and oscillator signals, and is zero at frequency lock. This is a division, of application Ser. No. 181,434, filed Sept. 17, 1971.
A flowmeter system having circuitry defining a path for confining the flow of a fluid medium therethrough, first and second transducers disposed along said flow path for generating and receiving acoustic compression waves in the fluid medium between the transducers, a phase lock loop receiver/transmitter system including a voltage controlled oscillator for adjusting the frequency of the acoustic compression waves to maintain the compression wave length constant, a phase detector for measuring the phase difference of the received acoustic compression waves relative to that transmitted and for producing a sum signal proportional to the sum of the measured phase differences to vary the output of said voltage controlled oscillator, circuitry for producing a difference signal proportional to the difference of the measured phase differences representing the direction and magnitude of the flow of the fluid medium as well as changes in its composition and an active filter in the loop for increasing the loop gain of thesystem.
A clock generator for digital demodulators is disclosed wherein a voltage-controlled oscillator (19) generates clock pulses at controlled frequency and phase in response to error signals from a phase comparator (14) and a frequency comparator (12). The phase error signal represents a phase deviation of the clock from a window pulse which is generated in response to a predetermined transition between binary "1"s and binary "0"s of an input bit stream. The frequency comparator detects the frequency of the clock pulse and compares it with lower and upper limits of a predetermined range of frequency variations and generates a frequency control signal having different voltages depending on the result of the comparison.
The invention relates to the synchronization of a frequency-controllable oscillator in a PLL circuit with a carrier. The adjustment of this oscillator to the carrier frequency can be dispensed with in that additionally a frequency discriminator is provided which initially tunes the oscillator in accordance with the frequency difference. The frequency discriminator compares each oscillator frequency with a stable reference frequency which is proximate to the desired frequency and tunes the oscillator until it is in the range of the reference frequency. Subsequently the frequency discriminator is blocked and the further synchronization is taken over by the phase discriminator in the PLL circuit.
Apparatus for the rapid monitoring of an alternating (a-c) variable with respect to amplitude, frequency and phase which includes a generator circuit for forming, from an actual a-c voltage imaging the monitored a-c variable, a reference a-c voltage of predetermined amplitude and frequency which is linked to the former in rigid phase relationship, and comparators for comparing individual signals of the generator circuit with the instantaneous values of the actual value a-c voltage, permitting recognition of disturbances in a time which is substantially shorter than one period of the a-c variable monitored.
A sidelock avoidance scheme for preventing sidelock in a PSK demodulator's carrier recovery loop contains augmenting sweep control circuitry, including a frequency discriminator and an associated window comparator. The output of the frequency discriminator, which is low pass filtered to remove noise, is applied to the window comparator which compares any differential between the true carrier and the output of a carrier recovery loop to a preset reference threshold representative of a frequency error condition that may approach sidelock. When the output of the frequency discriminator is greater that this preset reference threshold, an augmented frequency control voltage is applied to the voltage control oscillator of the loop to drive the oscillator away from a possible sidelock condition and toward the true carrier. The augmented frequency control voltage may be derived from a frequency sweep generator or from the output of the frequency discriminator, depending upon a selected strapping option.
