A demodulating system to be utilized in Secam television receivers for deriving the R-Y and B-Y chrominance information signals from the frequency modulated Secam RF subcarrier frequencies without the necessity for precise and stable tuned circuits. The demodulating system includes a single discriminator having an electronically tunable center frequency, a remodulator, for producing a reference frequency amplitude modulated by the chrominance information signals which are supplied to a commutator as known, and a feedback circuit coupled between the discriminator and remodulator. The discriminator is selectively tuned to a reference center frequency during each picture line clamp period to produce a zero level output signal. During the chrominance information portion of each line, the center frequency of the discriminator is alternately offset by first and second control signals to center frequencies coinciding with the two reference frequencies to produce a zero output level whenever the Secam signals are at the respective RF subcarrier frequencies. The feedback circuit ensures that the zero output levels obtained during the information carrying portion of each line is identical with the zero output level set during the clamp period.

A digital signal transmission system in which a pulse code modulated (PCM) signal is retimed in a regenerator using a decision circuit supplied by a clock, the frequency of which is half that of the bit rate (typically 1 Gigabit/second), and is demultiplexed using multiplexers clocked at a frequency half that of the bit rate. In each case the clock frequency is derived from the data stream using a clock extractor. A voltage controlled oscillator (VCO) generating a signal at substantially half the bit rate is connected to one input of a phase detector to another input of which is connected to receive current pulses representing transitions in the incoming data signal. The phase detector comprises first, second and third pairs of long tailed-pair connected transistors, the collectors of the transistors of the first pair of being connected respectively to the common connected transistors of second and third pairs. A first delay circuit providing a delay of approximately a quarter of a period of the VCO is connected between the base electrode of one of the first pair of transistors and the base electrode of one transistor of each of the second and third pairs of transistors. A second delay circuit of the same period as the first delay circuit is connected between the base electrode of the other of the first pair of transistors and the base electrode of the other transistor of each of the second and third pairs of transistors.

The signal phase detector according to this invention comprises a differential amplifier with a couple of transistors, a first transistor inserted between the emitters of the couple of transistors and a first point of reference potential, a second transistor inserted between the output terminal of one difference the transistors of the differential amplifier and a second point of reference potential, a third transistor connected to the second point of reference potential, and a fourth transistor connected in series with the third transistor and between the output terminal of the third transistor and the output terminal of the other of the transistors of the differential amplifier. A reference signal is applied to the base of the first transistor, while a signal to be compared is applied to the base of one of the transistors of the differential amplifier, so that an output signal corresponding to the phase differential between the two signals is obtained from the output terminal of the other of the transistors of the differential amplifier.