A generalized and modular logic circuit for arithmetic/logical units of a digital computer, adaptable to large scale integration (LSI) manufacturing techniques. Each logic circuit includes combinational logic networks which provide inputs to storage circuitry. The storage circuitry is sequential in operation and employs clocked dc latches. Out-of-phase clock trains are used to control the latches. With each storage circuit, there is provided additional circuitry for providing an input which is independent of the combinational logic network. A logic unit comprised of a plurality of the logic circuits is constructed to interconnect the output of a storage circuit to the independent input of another logic circuit so that each latch acts as one position of a shift register having inputs/outputs independent of the system inputs/outputs.
Disclosed is a novel device, named the Accordion Shift Register (A.S.R.) by virtue of an alternative expansion-compaction behavior of the digital data as it passes through the device. The A.S.R. provides an economical substitute for the conventional L1/L2 type Shift register used in a large scale integrated (LSI) logic structures known as the Level Sensitive Scan Design (LSSD). (See U.S. Pat. No. 3,783,254).
A shift register which is formed by a memory, the number of shift stages of the shift register is determined by the count value of a counter and designating a read address of the memory by a value obtained by subtracting an arbitrary constant from the count value of the counter through an operator. A multiplexer is provided at the input side of the operator. Output data, obtained by selecting a constant for determining the number of shift stages of the counter and a scan address in accordance with a scan enable signal, are provided to the operator. When the constant for determining the number of shift stages of the counter is input, the operation of the shift register is carried out and when the scan address is input, the content of each stage of the shift register is scanned out.
A latch circuit possesses a scan capability, has a single clock input line, and possesses a locking feature whereby input data, once locked in the latch, is insensitive to further changes in state of the input data. The latch also possesses a novel selection apparatus which functions to select either a scan data input line or a system data input line in accordance with the binary state of a system gate input line, the selection apparatus developing an output signal, the binary state of which is locked in the latch in response to a predetermined state of a clock pulse conducted via the single clock line. Clock skew compensation is provided via the locking feature. During a scan mode, clock skew compensation is provided when the clock pulse is received for a period of time after termination of reception of a scan pulse conducted via the system gate input line.
Addressing control apparatus is structured to provide either byte or word addressing of storage organized on a word basis. The storage address register is made shiftable whereby for byte operations, it is shifted, and the bit shifted out of the register is used for byte selection. The contents of the storage address register are used to address storage for both word and byte addressing, and no change is required. The storage access, however, for byte addressing takes place after the shift is completed and the timing is adjusted to account for the shift operation. Gate control logic is modified to facilitate the byte selection.
A semiconductor integrated circuit has a test circuit in which signal pad (15) to input a switching signal TM is formed on a non-mounting surface of a LSI and one group of signal pads (11 to 13) formed on the non-mounting surface and signal pads (16 to 18) formed on a mounting surface is selected based on a signal level of the switching signal TM.
