A phase locked loop provides frequency modulation over an extended frequency range by summing a modulation signal with the loop signal at two separate points within the loop. The modulation signal is directly applied to the control input terminal of the voltage controlled oscillator. In addition, the modulation signal is processed to compensate for the transfer functions of loop components, and the processed signal is summed with the loop signal at an additional point between the output terminals of the phase detector and the lowpass filter of the loop. The processing of the modulation signal consists of preshaping of the signal to compensate for the transfer functions of loop circuitry located between the voltage controlled oscillator and the summing junction.

A receiver having an RF section, a mixer stage and a signal processing stage, the mixer stage receiving a mixing frequency from a frequency synthesis circuit which includes a phase-locked loop provided with a phase detection device having a current output, a loop filter including a .pi.-shaped RC network having an input shunt path and an output shunt path which are connected to respective ends of a series resistor incorporated in a series path, and to ground, and include first and second capacitances, respectively, and with a voltage-controlled oscillator, a reference frequency being applied to the phase detection device. In order to prevent the use of active filter circuits in the phase-locked loop of such a receiver, the second capacitance is chosen to be at least twice as large as the first capacitance, the series resistance is chosen to be smaller than the output impedance of the phase detection device and the output shunt path of the loop filter is provided with an RC phase shift member for reducing the phase shift of the second capacitance in the output shunt path.

There is disclosed a phase locked loop transmitter modulated by modulating signals. This transmitter includes a controlled oscillator providing a first frequency signal, a two-input phase detector whose output is coupled to the controlled oscillator for frequency control thereof, a mixer and a source of second frequency signal. All of these transmitter components are associated with the phase locked loop and at least the phase detector and the controlled oscillator are incorporated as part of the loop. The modulating signals are coupled to the controlled oscillator through the phase detector.

A transmitter transmitting signal bursts to a TDMA communication system, and comprising a frequency synthesizing circuit having an input on which a bit flow is received, and an output on which a data-modulated output signal is supplied, a controller controlling the transmission of the transmitter and a stable clock signal generator supplying a stable clock signal. The frequency synthesizing circuit includes a phase-locked loop (PLL) comprising a voltage controlled oscillator (VCO) and a phase detecting unit. The voltage controlled oscillator (VCO) generates an output signal whose frequency is controlled by a control signal, said output signal being modulated in response to the data bit flow received on the input. The phase detecting unit compares the output signal supplied by the voltage controlled oscillator with the stable clock signal supplied by the stable clock signal generator and supplies an error signal in response thereto. A compensating circuit which receives a measure of the bit flow received, compensates the error signal for contributions originating from the bit flow received, and supplies the compensated error signal as a control signal to the voltage controlled oscillator (VCO). The transmitter furthermore includes swithing means controlled by said controller for resetting said error signal before the transmision of a burst.

A signal generator includes an oscillator, a phase locked loop and a fractional divider. The oscillator is configured to provide an output signal. The phase locked loop is configured to receive the output signal and to provide a tuning signal to the oscillator. The phase locked loop has a phase detector configured to receive the output signal, to compare the output signal to a reference signal, and to provide the tuning signal to the oscillator based on the comparison. The fractional divider is outside of the phase locked loop and is configured to generate the reference signal.