The instant invention relates to a unique logic network whereby data into and out of the memory array of a specialized digital computer will be permuted such that the data will maintain a convenient and consistent order on a data interface. The network may be constructed using commonly-available n-channel data selectors. Fundamentally, the invention functions in conjunction with a digital computer memory array whose data storage pattern is such that accesses to the stored data may be made in word-oriented mode, bit-oriented mode, or mixed-oriented mode, the latter comprising characteristics of the two aforementioned modes. The invention requires a minimum amount of extra-network control circuitry, and comprises a plurality of uniquely identical smaller networks of such size that they may be readily packaged on individual printed circuit boards such that a minimum of interboard wire connections are necessary. Further, the similarity of smaller networks facilitates maintainability of the entire network.
A data storage apparatus comprises a memory circuit including 2.sup.n1.multidot.n2 memories for storing binary information. Data of N bits from the row direction and column direction can be written and read out in parallel, and, also, such data of N bits reduced with a data reduction rate of an exponential power of 2 can be written and read out in parallel. The apparatus is used, for example, for displaying data on a display by fetching the data from common file servers connected to a private network or the like.
A data memory arrangement includes n columns of storage elements each column being addressable only one element at a time and having at least n.sup.2 storage elements so as to provide a succession of square arrays. Each square array comprises square sub-sections. On storage of a complementary array of data the data is multiplexed from each square array to the next within each sub-section and after each cycle of such multiplexing the sub-sections are rotated one step cyclically. Such rearrangement of data gives freedom and speed of simultaneous access to data words occurring in original rows and/or columns without excessive penalty in the complexity of the addressing system.
A table translator circuit arrangement comprises a plurality of random access word organized memories, input circuitry, output circuitry, and control circuitry. The word locations of each memory are separated into control and data locations defined by corresponding ranges of memory access addresses. Each table entry comprises one or more access control bits and associated data. Each table address defines a control location in one memory of the plurality and data locations in additional memories of the plurality. An entry to be written into the table is provided to input rotate circuitry which is controlled by a portion of the table address which defines the location at which the entry is to be written. The input rotate circuitry delivers the access control bits of the entry to a memory in which a control location is accessed and delivers the associated data bits to additional memories in which data locations are accessed. When an entry is read from the table, the address corresponding to that entry is utilized to access the control and data locations containing the entry. An entry read from the table is provided to output rotate circuitry which is controlled by a portion of the table address which defines the location from which the entry is read. The output rotate circuitry reassociates the access control bits and the associated data bits to their original format. To rapidly clear the memory locations which can contain access control bits, all memory addresses which define control locations are sequentially accessed in parallel in all memories of the plurality. An address generator which defines the memory addresses at which control bits can be stored is stepped sequentially through those addresses and as each address is utilized, the control bits at those locations are cleared. Accordingly, a control location is simultaneously cleared in each of the memories of the plurality thereby dividing by the number of memories the time necessary to clear the table locations which can contain access control bits.
The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.
A method and system are disclosed for efficiently translating data from one known data sequencing arrangement to an alternative sequencing arrangement. The method consists of the steps of generating a source sequence signal which identifies the ordering of units within the source sequence, generating a destination sequence signal which identifies the ordering of units within the destination sequence, and combining the source signal and destination signal to produce a permutation signal which defines the relationship between the source sequence and the destination sequence. Once the permutation signal has been defined, this permutation signal is applied to the source sequence to allow the reordering of the source sequence into the desired destination sequence. A reordering circuit is used to rearrange the source sequence units into the desired destination sequence units utilizing the permutation signal generated in the present invention. The reordering circuit consists of an array of ordered swap units which contain inputs for source sequence signals and permutation signals, and outputs which propagate destination sequences.
