A configuration and control unit (CACU) is described for a multi-system containing processors, which may be of different types, with heterogeneous channels and local and remote devices, including channel crossbar switches, I/O channel switches, I/O control units and I/O units. The CACU is the focal point in the multi-system for configuration, maintenance and special control over the multi-system. The CACU contains a PWL adapter to control local devices, and a time multiplexed (TM) adapter to control remote devices. Time multiplexed lines (TML's) connect the TM adapter to remote modem adapters (RM's) located with remote devices. Each RM includes a configuration register, control register and maintenance register. These registers are connected between a modem in the RM and its associated device. These registers are operated by CACU commands to store the connection path between the remote device and any processor, communicate the connection path to the CACU on CACU command, provide special control for the device on command, and receive maintenance status from the device for communication to the CACU on command. Normal data to or from a remote device from a processor may pass through its RM adapter or may have a separate data path. Persistent storage devices are optionally providable in the RM for persistently storing the configuration signals currently in the configuration register. Upon failure of any item in the stored configuration path, the settings in the persistent storage devices can recover the connecton path for the remotely controlled device in the multi-system.

A radiation hardened register file renders a central processing unit intrinsically hard to the disruptive effects of nuclear radiation by providing means for establishing a valid rollback point for each computer instruction operation performed in the central processing unit. Dual data register images provide alternate locations for storing data operands in the register file. A pointer register stores a signal the truth state of which indicates which of the two images currently provides the proper place to store information presently being written and also provides an indication of the current location of assured valid signals for a recovery operation and resumption of normal computer functions subsequent to a disruptive event. Pointer save registers are used to store the latest value of the signal stored in the pointer registers, thereby also preserving valid pointer information for recovery subsequent to a circumvented disrupting event. A master pointer register stores a signal indicating which of two alternate pointer save registers currently stores the appropriate signal for selecting the proper truth state for the signal in the pointer register.

A loop circuit interface module enabling a plurality of data terminals remote from each other and from a central controller to communicate with each other and the central controller over a plurality of data channels interconnecting same is disclosed. The loop circuit interface module comprises a plurality of data ports for inputting data from either the loop controller or another loop circuit interface module. The data ports also output data to the loop controller or another loop circuit interface module. The module has a plurality of signal ports for inputting data from the data terminal and for outputting data to the data terminal. A bridging means provides a matched impedance between the loop circuit interface module, the loop controller, and the data terminals. The bridging further provides gain to the data at the plurality of ports. Switching means selectively and controllable connects the plurality of data ports and the plurality of signal ports directly to each other, or to each other through the bridging means.

The invention relates to a process for dynamically reconfiguring an information processing system (1), particularly a so-called "SMP" symmetric multiprocessor system. The process comprises a preliminary step for detecting a failure risk of one of the components of the system (CPU3). Following this detection, the system (1) is placed in a coherent, so-called "frozen" state in a first step with the aid of programs (J1-J4) executing specific tasks. A second step consists of reconfiguring the system by reallocating/de-allocating all or some of the components (CPU1-CPU4). In a third step, the component (CPU3) that presents a failure risk is isolated. The pending interruptions (4) are processed and the current tasks (6) are executed prior to the "freeze." Likewise, the queues of tasks to be executed are purged prior to the "freeze." Then, the subsequent tasks and interrupts are inhibited until a final step that consists of releasing the system (1).

In an information processing system for use in detecting an error in a main memory (11) comprising a plurality of memory units (111 to 118) and a common control section (19), an error detection signal and an error address are sent from a request source processor (15) to a diagnostic address generator (31) when an error is detected on an access operation of the request source processor. On diagnostic access operations, the diagnostic address generator successively produces a plurality of diagnostic addresses including the error address to receive diagnostic replies, each of which comprises a reply code. When an error of the main memory is indicated by the reply code, an error detection controller (32) discriminates the diagnostic address on occurrence of the error in the diagnostic operations to disconnect the memory unit or units from the main memory by the use of a memory restructuring circuit (36). All of the memory units are disconnected when a malfunction of the common control section is discriminated by the error detection controller.