The disclosure described improved apparatus for testing a data processing system including first and second functional members. First and second microprograms for testing the first and second functional members, respectively, are held in a read only store. If an error is detected in the first functional member while the data processing system is processing data, a circuit transmits the starting address of the first microprogram to an address register for the store, so that the first microprogram tests the defective first functional member. As the first functional member is tested, the symptoms needed to diagnose the defect are collected. If the first microprogram is completed without all of the symptoms required for diagnosis being collected, another circuit transmits the first address to the address register so that the first microprogram is executed again. The first microprogram continues to be executed until all of the symptoms needed for diagnosis are collected. The same procedure is used for the testing of the second functional member.

A method for analyzing the operation of a microprocessor connected to a system to be tested and a plurality of buses includes the following steps. From the information concerning bus signal states and instruction execution, only information for cases other than interrupt routine processes and subroutine processes is selected, and the selected information is stored into a memory device, and then an analysis of the operation of the microprocessor on the basis of the selected and stored information is carried out. Alternatively, from the information concerning bus signal states and instruction execution, only information for cases other than executions of a stack pointer changing instructions and interrupt response processes is selected, and the selected information is stored into a memory device, and then an analysis of operation of the microprocessor on the basis of the selected and stored information is carried out. Apparatuses for these methods are also disclosed.

A programmable fault injection tool (PFIT) for the texting of the diagnostic capabilities of a computer or digital processing system is disclosed. The PFIT is made up of event compare hardware and error injection hardware. The event compare hardware of the PFIT is user programmable through menu-driven software to compare a particular stored event, either a digital word or sequence of words, with an event measured within the system under test. The stored event can be changed by the user under program control so as to provide a generalized fault injection tool. In addition, the tool includes a mask memory that allows certain bits in a word to be masked, or ignored, when the state of the bit within the word is inconsequential. The error injection hardware of the PFIT is controlled by the event compare hardware to inject faults by short circuiting voltage nodes within the system under test to ground or a supply voltage. The error injection hardware will inject the fault for a user specified time duration and only after a user specified time delay.

A method of testing a memory containing data being used by a processor uses a dedicated diagnostic test page (DTP) and diagnostic status page (DSP) in the memory under test to carry out the testing. The DTP is address-tested and pattern-tested first. Then, each page of the memory is in turn copied to the DTP, tested, and then restored from the DTP. During the test, the address of the page being tested is stored in the DSP along with a valid flag and an error detection code (EDC). A recovery procedure uses the information on the DSP to restore memory pages if the test is interrupted.

Diagnostic apparatus couples to a control store of a microprogrammed peripheral processor and is used to cycle the store in a plurality of different modes. The diagnostic apparatus includes mode control circuits which when set to a first mode, cause an instruction bit pattern established by a plurality of switches to be loaded into the local register of the control store when the apparatus detects that a predetermined address established by a set of address switches of the apparatus compares to the address stored in the address register of the control store. During the following cycle, the switch established instruction bit pattern substituted for the instruction stored at the location designated by the address switches is executed. When the diagnostic apparatus is set to operate in a second mode, the switches are set to establish a branch type instruction containing an address corresponding to a starting address in the store to be repeated of a microprogram routine. Each time the diagnostic apparatus detects a comparison, it forces the store and processor to a known state. During a following cycle, the microinstruction is loaded into the local register and executed causing the store to branch to the routine specified for execution.