In order to improve yield, integrated circuits may advantageously be tested using internal test circuitry during fabrication to locate faults. In order to conduct the necessary tests without providing an extra external test connection, the invention contemplates using a required existing terminal of an integrated circuit along with a test circuit which is activated by a voltage outside the normal operating voltage range, such as a voltage of opposite polarity to that used during normal operation.

A shift register connected to elementary gates is added to a digital network to form a fault simulator. The shift register and the additional gates can select a connection from the digital network and simulate a fault on the selected connection. Connection selection is done at a speed comparable to that at which the digital network operates and fault simulation is nondestructive. By resetting the shift register the fault simulator performs as if the digital network were fault-free. To simulate certain faults in the digital network a predetermined fault injection pattern for the faults to be simulated is entered into the shift register.

A semiconductor device with a monitor pattern and a method for monitoring device parameters. The monitor pattern comprises a semiconductor layer, a first region, a second region and a third region. The first region is formed in the semiconductor layer. The second region is formed within the first region so that the surface of the first region is divided into two portions. The third region is formed in the semiconductor layer and electrically connected to the substrate. One of the two portions of the first region is electrically connected to the third region. As the second region becomes deeper, the connection (lying beneath the second region) which connects the two portions of the first region becomes thinner. As this connection becomes thinner, its resistance is increased. Thus, monitoring of resistance between the two portions of the first region provides an index of the depth of the second region, and thereby of doping profile change during manufacture.

Method and circuit for checking integrated circuit chips without the use of external checking circuits. Chips are fabricated with an error-checking circuit on each chip. Data from data processing logic on each chip is outputted via a first path to one input of its respective checking circuit and via a second path to an output pin or pins. The output pin on each chip is also connected via a third path to the other input of its checking circuit. The input and output pins of each chip are wired in parallel. A separate check input pin is provided to each integrated circuit chip. On one chip this pin is activated, making this first chip the checker. On the other chip, the check input pin is deactivated. On the chip which is the checker, the output from the data processing logic is prevented from being passed externally via the first path, but is allowed to enter the checking circuit via the second path. The output from the other chip, which is wired in parallel with the first chip, enters the error-checking circuit on the first chip via the third path. The outputs from the first chip and the second chip are thus checked with respect to each other in the error-checking circuit, and if they do not check properly an error output is generated, indicating that one of the data processing logic circuits is faulty.

A large-scale integrated circuit chip includes a plurality of bistables connected to combinational logic. In a diagnostic mode, the bistables are operated as a serial shift register, allowing test data to be shifted through the chip between diagnostic input and output pins (LPIN,LPOUT). In a chip test mode, the serial shift register is split into a number of shift register portions, each of which is connected between a separate pair of input and output pins. This allows test data to be shifted through all the shift register portions in parallel so as to speed up testing of the chip.