An electronic digital processor which may be used in a hand-held calculator is implemented in a single MOS/LSI semiconductor chip. The processor includes a ROM for storing instruction codes, a RAM for storing data, an arithmetic unit for performing operations on data under control of micro-instructions or commands, and control circuitry including a decoder for generating the commands in response to the instruction codes. The arithmetic unit is controlled by a group of micro-instructions generated from a certain class of instruction codes, while another class of instruction codes includes fields for constants used in some operations such as "compare contents of accumulator with a constant." The class of instructions for controlling the arithmetic unit is directly coupled to a decoder for generating the microinstructions, while the class containing constants is "faked" or indirectly coupled to the decoder through a converter which changes the instruction codes to resemble the ones which control the arithmetic unit. Some of the bit positions which define the constant may, through conversion, be used to generate microinstructions. This arrangement is more efficient in utilization of space on the chip, for a given instruction set.

In a digital electronic computer which comprises a memory including a first and a second register, the first register is receptive of a number to be converted from fixed to floating point notation and the second register is receptive of a significant zero digit with an associated decimal point. Shifting means including a register is operable to shift the contents of either register and aligning means is operable to cause shifting of the second register until the decimal point stored therein is aligned with the decimal point in the first register. Indicating means indicates whether the number stored in the first register is greater or less than one and the shifting means next begins shifting the contents of one or the other of the registers when the number is indicated greater or less than one respectively. A control means includes a detecting means for stopping the shifting means when the decimal point of the second register becomes aligned with the location of the next higher order with respect to the highest significant digit of the first register. The control means also includes counting means which is incremented or decremented by one for each shifting operation in dependence on the direction of shifting. The resultant numbers in the first and and second registers represent the mantissa and exponent respectively, of the desired floating point number.

A digital processor which may be used in a calculator or the like is provided by an MOS/LSI semiconductor chip which contains a ROM or read-only-memory for storing instructions, a bit-parallel arithmetic unit for operating on data stored in a random access memory and control circuitry for defining the operation of the system. The control circuitry includes a programmable logic array for decoding instruction words. Space on the chip is saved by a time-shared decoder which forms part of the programmable logic array and also decodes addresses for the ROM.

A digital computer wherein data words representing different data types, such as fixed point numbers, floating point numbers of logical statements, are retrieved from memory in any order required during execution of a program and, after conversion to a predetermined format, are applied to an arithmetic unit for processing. To accomplish the conversion, logic circuitry is provided to identify, during execution of a program, the data type of each retrieved data word and to change the format of each such word to the predetermined format for processing in the arithmetic unit. Additional logic circuitry is provided to respond to each data word out of the arithmetic unit to reconvert each such word back into a format for storage in memory.

A data-processing system for pattern-recognition and the like, having an instruction unit (IU) for storing, decoding and modifying instructions, and an execution unit (EU) for storing and performing operations on data. The IU has facilities for making a branch address effective for a plurality of subsequent instructions, and for masking and de-conditioning the prospective branch. The IU also indexes data-operand addresses according to a variable modulus. The EU performs Boolean and voting logic functions in a series of cascaded registers. The EU controls the acquisition of external data according to the type of instruction being executed, and maintains a record of the location of data strings in memory. Intermediate computational results are automatically placed in a hardware stack without any programming overhead. Bits from multiple operands are placed in a single operand byte by shift-load instructions.